From 80e9d2cea9198b38f62a68bc420328222b3b6709 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 27 Jul 2021 16:57:08 +0200 Subject: [PATCH] soc/interconnect/stream: Support n=1 case on Multiplexer/Demultiplexer. Required by LiteSPI when only one Core is connected to the PHY (ex when disabling Master or MMAP). --- litex/soc/interconnect/stream.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index a11ab191d..0c2654b22 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -266,7 +266,7 @@ class Multiplexer(Module): sink = Endpoint(layout) setattr(self, "sink"+str(i), sink) sinks.append(sink) - self.sel = Signal(max=n) + self.sel = Signal(max=max(n, 2)) # # # @@ -284,7 +284,7 @@ class Demultiplexer(Module): source = Endpoint(layout) setattr(self, "source"+str(i), source) sources.append(source) - self.sel = Signal(max=n) + self.sel = Signal(max=max(n, 2)) # # #