From 81be74a7b1420030b279bd907138a5804fe9203c Mon Sep 17 00:00:00 2001
From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Mon, 30 Mar 2020 13:43:34 +0200
Subject: [PATCH] targets: netv2: add LiteSPI

---
 litex/boards/targets/netv2.py | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 3bb14c561..5ac6b2306 100755
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -13,12 +13,16 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.integration.soc import *
 
 from litedram.modules import K4B2G1646F
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.rmii import LiteEthPHYRMII
 
+from litespi import LiteSPI
+from litespi.phy.generic import LiteSPIPHY
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -46,7 +50,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_spi_xip=False, **kwargs):
         platform = netv2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -72,6 +76,14 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
+        # SPI XIP ----------------------------------------------------------------------------------
+        if with_spi_xip:
+            spi_xip_size = 1024*1024*8
+            self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
+            self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
+            spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
+            self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
+
         # Ethernet ---------------------------------------------------------------------------------
         if with_ethernet:
             self.submodules.ethphy = LiteEthPHYRMII(
@@ -88,9 +100,11 @@ def main():
     soc_sdram_args(parser)
     parser.add_argument("--with-ethernet", action="store_true",
                         help="enable Ethernet support")
+    parser.add_argument("--with-spi-xip", action="store_true",
+                        help="enable SPI XIP support")
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()