From 8254a349f847f8b1abb1c84b72f6f259ea2d8f69 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 19 Dec 2024 17:59:58 +0100 Subject: [PATCH] build/vhd2v_converter.py: fix params vs instance when conversion is disabled --- litex/build/vhd2v_converter.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/build/vhd2v_converter.py b/litex/build/vhd2v_converter.py index 6047ba7bd..84e280054 100644 --- a/litex/build/vhd2v_converter.py +++ b/litex/build/vhd2v_converter.py @@ -138,7 +138,10 @@ class VHD2VConverter(Module): # platform able to synthesis verilog and vhdl -> no conversion if self._platform.support_mixed_language and not self._force_convert: - ip_params = self._params + if self._params: + ip_params = self._params + else: + ip_params = self._instance.items for file in self._sources: self._platform.add_source(file, library=self._work_package) else: # platform is only able to synthesis verilog -> convert vhdl to verilog