From 838719c276f6df3be2fcfb080b59eacc15574972 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Feb 2023 11:34:13 +0100
Subject: [PATCH] cores/xadc: Re-arrange and simplify code a bit.

---
 litex/soc/cores/dna.py | 38 ++++++++++++++++++++++++++++----------
 1 file changed, 28 insertions(+), 10 deletions(-)

diff --git a/litex/soc/cores/dna.py b/litex/soc/cores/dna.py
index 5d515bba6..d606fbc68 100644
--- a/litex/soc/cores/dna.py
+++ b/litex/soc/cores/dna.py
@@ -5,31 +5,41 @@
 # Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
+import math
+
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.interconnect.csr import *
 
 
 # Xilinx DNA (Device Identifier) -------------------------------------------------------------------
 
-class DNA(Module, AutoCSR):
-    nbits = 57
-    def __init__(self):
-        self._id = CSRStatus(self.nbits)
+class XilinxDNA(Module, AutoCSR):
+    def __init__(self, nbits=57, primitive="DNA_PORT", clk_divider=16):
+        self.nbits       = nbits
+        self.clk_divider = clk_divider
+        self._id = CSRStatus(nbits)
 
         # # #
 
-        # Create slow DNA Clk (sys_clk/16).
+        # Parameters check.
+        assert nbits      <= 256
+        assert clk_divider > 1
+        assert math.log2(clk_divider).is_integer()
+
+        # Create slow DNA Clk.
         self.clock_domains.cd_dna = ClockDomain()
-        dna_clk_count = Signal(4)
+        dna_clk_count = Signal(int(math.log2(clk_divider)))
         self.sync += dna_clk_count.eq(dna_clk_count + 1)
-        self.sync += self.cd_dna.clk.eq(dna_clk_count[3])
+        self.sync += self.cd_dna.clk.eq(dna_clk_count[-1])
 
 
         # Shift-Out DNA Identifier.
         count = Signal(8)
         dout  = Signal()
-        self.specials += Instance("DNA_PORT",
+        self.specials += Instance(primitive,
             i_CLK   = ClockSignal("dna"),
             i_READ  = (count == 0),
             i_SHIFT = 1,
@@ -37,12 +47,20 @@ class DNA(Module, AutoCSR):
             o_DOUT  = dout,
         )
         self.sync.dna += [
-            If(count < (self.nbits + 1),
+            If(count < (nbits + 1),
                 count.eq(count + 1),
                 self._id.status.eq(Cat(dout, self._id.status))
             )
         ]
 
     def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
-        platform.add_period_constraint(self.cd_dna.clk, 16*1e9/sys_clk_freq)
+        platform.add_period_constraint(self.cd_dna.clk, self.clk_divider*1e9/sys_clk_freq)
         platform.add_false_path_constraints(self.cd_dna.clk, sys_clk)
+
+# Xilinx 7-Series DNA ------------------------------------------------------------------------------
+
+class S7DNA(XilinxDNA):
+    def __init__(self, *args, **kwargs):
+        XilinxDNA.__init__(self, nbits=57, primitive="DNA_PORT", *args, **kwargs)
+
+class DNA(XilinxDNA): pass # Compat.