diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 63a6ea449..fbae4668f 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -48,14 +48,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = arty.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - integrated_sram_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -81,7 +78,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 553a2f2ab..b9385f2d7 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM): platform = de0nano.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 7bb495dcb..1d685c750 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -41,14 +41,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = genesys2.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -74,7 +71,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 871607210..c34b1ab0b 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -43,14 +43,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kc705.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -76,7 +73,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 1243454fa..ff78579cf 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -81,10 +81,7 @@ class BaseSoC(SoCSDRAM): platform = kcu105.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -111,7 +108,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 04f71c592..e67c16da9 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -49,9 +49,7 @@ class BaseSoC(SoCSDRAM): platform = minispartan6.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 7fecb76ab..90bdba024 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -46,14 +46,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = netv2.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -79,7 +76,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index e19c6f3a4..8999603e5 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -45,14 +45,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys4ddr.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index fa423ac62..b00c1886d 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -45,14 +45,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex/boards/targets/pcie_screamer.py b/litex/boards/targets/pcie_screamer.py index 809d051a6..f94d40fe1 100755 --- a/litex/boards/targets/pcie_screamer.py +++ b/litex/boards/targets/pcie_screamer.py @@ -39,14 +39,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = pcie_screamer.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - integrated_sram_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 877719ea6..d04dd8d28 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -19,14 +19,12 @@ from liteeth.mac import LiteEthMAC # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, platform, integrated_rom_size=0x8000, **kwargs): + def __init__(self, platform, **kwargs): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - integrated_main_ram_size=16*1024, - **kwargs) + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) @@ -38,7 +36,7 @@ class EthernetSoC(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, platform, integrated_rom_size=0x10000, **kwargs): + def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 94994a77f..0869069bb 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -55,9 +55,7 @@ class BaseSoC(SoCSDRAM): sys_clk_freq = int(50e6) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 87125712a..fe3f0e1e8 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -72,13 +72,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -105,7 +103,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, toolchain="diamond", **kwargs): - BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, toolchain=toolchain, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 6592e1a27..8bd25f2c9 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -85,7 +85,7 @@ class SoCCore(Module): # CPU parameters cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, # ROM parameters - integrated_rom_size=0, integrated_rom_init=[], + integrated_rom_size=32768, integrated_rom_init=[], # SRAM parameters integrated_sram_size=4096, integrated_sram_init=[], # MAIN_RAM parameters @@ -560,13 +560,13 @@ def soc_core_args(parser): parser.add_argument("--cpu-reset-address", default=None, type=int, help="CPU reset address (default=0x00000000 or ROM)") # ROM parameters - parser.add_argument("--integrated-rom-size", default=None, type=int, + parser.add_argument("--integrated-rom-size", default=0x8000, type=int, help="size/enable the integrated (BIOS) ROM") parser.add_argument("--integrated-rom-file", default=None, type=str, - help="integrated (BIOS) ROM binary file") + help="integrated (BIOS) ROM binary file (default=32KB)") # SRAM parameters - parser.add_argument("--integrated_sram_size", default=None, - help="size/enable the integrated SRAM") + parser.add_argument("--integrated_sram_size", default=0x1000, + help="size/enable the integrated SRAM (default=4KB)") # MAIN_RAM parameters parser.add_argument("--integrated-main-ram-size", default=None, type=int, help="size/enable the integrated main RAM")