From 84b5df78711cd67f3bfa0784df7142748fcbf44d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 9 Feb 2020 21:56:32 +0100
Subject: [PATCH] soc: add add_cpu method

---
 litex/soc/integration/soc.py      | 26 ++++++++++++++++
 litex/soc/integration/soc_core.py | 50 ++++---------------------------
 2 files changed, 32 insertions(+), 44 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 51d08aa37..14edd3508 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -7,6 +7,7 @@ import datetime
 
 from migen import *
 
+from litex.soc.cores import cpu
 from litex.soc.cores.identifier import Identifier
 from litex.soc.cores.timer import Timer
 
@@ -689,6 +690,31 @@ class SoC(Module):
         self.csr.add("uart", use_loc_if_exists=True)
         self.irq.add("uart", use_loc_if_exists=True)
 
+    def add_cpu(self, name="vexriscv", variant=None, reset_address=None):
+        variant = "standard" if variant is None else variant # FIXME
+        if name not in cpu.CPUS.keys():
+            self.logger.error("{} CPU not supported, supporteds: {}".format(
+                colorer(name, color="red"),
+                colorer(", ".join(cpu.CPUS.keys()), color="green")))
+            raise
+        # Add CPU + Bus Masters + CSR + IRQs
+        self.submodules.cpu = cpu.CPUS[name](self.platform, variant)
+        self.cpu.set_reset_address(reset_address)
+        for n, cpu_bus in enumerate(self.cpu.buses):
+            self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
+        self.add_csr("cpu", use_loc_if_exists=True)
+        for name, loc in self.cpu.interrupts.items():
+            self.irq.add(name, loc)
+        if hasattr(self, "ctrl"):
+            self.comb += self.cpu.reset.eq(self.ctrl.reset)
+        # Update SoC with CPU constraints
+        self.soc_mem_map.update(self.cpu.mem_map)       # FIXME
+        self.soc_io_regions.update(self.cpu.io_regions) # FIXME
+        # Define constants
+        self.add_config("CPU_TYPE",       str(name))
+        self.add_config("CPU_VARIANT",    str(variant.split('+')[0]))
+        self.add_config("CPU_RESET_ADDR", reset_address)
+
     # SoC finalization -----------------------------------------------------------------------------
     def do_finalize(self):
         self.logger.info(colorer("-"*80, color="bright"))
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index d5feb9990..4626e5596 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -123,56 +123,18 @@ class SoCCore(SoC):
             self.add_controller("ctrl")
 
         # Add CPU
-        self.add_config("CPU_TYPE", str(cpu_type))
         if cpu_type is not None:
-            if cpu_variant is not None:
-                self.add_config("CPU_VARIANT", str(cpu_variant.split('+')[0]))
-
-            # Check type
-            if cpu_type not in cpu.CPUS.keys():
-                raise ValueError(
-                    "Unsupported CPU type: {} -- supported CPU types: {}".format(
-                        cpu_type, ", ".join(cpu.CPUS.keys())))
-
-            # Declare the CPU
-            self.submodules.cpu = cpu.CPUS[cpu_type](platform, self.cpu_variant)
-            if cpu_type == "microwatt":
-                self.add_constant("UART_POLLING")
-
-            # Update Memory Map (if defined by CPU)
-            self.soc_mem_map.update(self.cpu.mem_map)
-
-            # Update IO Regions (if defined by CPU)
-            self.soc_io_regions.update(self.cpu.io_regions)
-
-            # Set reset address
-            self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address)
-            self.add_config("CPU_RESET_ADDR", self.cpu.reset_address)
-
-            # Add CPU buses as 32-bit Wishbone masters
-            for cpu_bus in self.cpu.buses:
-                self.add_wb_master(cpu_bus)
-
-            # Add CPU CSR (dynamic)
-            self.add_csr("cpu", use_loc_if_exists=True)
-
-            # Add CPU interrupts
-            for _name, _id in self.cpu.interrupts.items():
-                self.add_interrupt(_name, _id)
-
-            # Allow SoCController to reset the CPU
-            if with_ctrl:
-                self.comb += self.cpu.reset.eq(self.ctrl.reset)
-
-            assert csr_alignment <= self.cpu.data_width
-            csr_alignment = self.cpu.data_width
+            self.add_cpu(
+                name          = cpu_type,
+                variant       = cpu_variant,
+                reset_address = self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address)
         else:
             self.submodules.cpu = cpu.CPUNone()
             self.soc_io_regions.update(self.cpu.io_regions)
 
         # Add user's interrupts (needs to be done after CPU interrupts are allocated)
-        for _name, _id in self.interrupt_map.items():
-            self.add_interrupt(_name, _id)
+        for name, loc in self.interrupt_map.items():
+            self.irq.add(name, loc)
 
         # Add integrated ROM
         if integrated_rom_size: