diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 025379a77..afd856c06 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -33,6 +33,8 @@ from litex.build.tools import get_litex_git_revision
 #                                     BANNER/TRAILER/SEPARATORS                                    #
 # ------------------------------------------------------------------------------------------------ #
 
+_tab = "\n"
+
 def _print_banner(filename, device):
     return """\
 // -----------------------------------------------------------------------------
@@ -283,7 +285,7 @@ def _print_node(ns, at, level, node, target_filter=None):
             assignment = " = "
         else:
             assignment = " <= "
-        return "\t"*level + _print_expression(ns, node.l)[0] + assignment + _print_expression(ns, node.r)[0] + ";\n"
+        return _tab*level + _print_expression(ns, node.l)[0] + assignment + _print_expression(ns, node.r)[0] + ";\n"
 
     # Iterable.
     elif isinstance(node, collections.abc.Iterable):
@@ -291,29 +293,29 @@ def _print_node(ns, at, level, node, target_filter=None):
 
     # If.
     elif isinstance(node, If):
-        r = "\t"*level + "if (" + _print_expression(ns, node.cond)[0] + ") begin\n"
+        r = _tab*level + "if (" + _print_expression(ns, node.cond)[0] + ") begin\n"
         r += _print_node(ns, at, level + 1, node.t, target_filter)
         if node.f:
-            r += "\t"*level + "end else begin\n"
+            r += _tab*level + "end else begin\n"
             r += _print_node(ns, at, level + 1, node.f, target_filter)
-        r += "\t"*level + "end\n"
+        r += _tab*level + "end\n"
         return r
 
     # Case.
     elif isinstance(node, Case):
         if node.cases:
-            r = "\t"*level + "case (" + _print_expression(ns, node.test)[0] + ")\n"
+            r = _tab*level + "case (" + _print_expression(ns, node.test)[0] + ")\n"
             css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)]
             css = sorted(css, key=lambda x: x[0].value)
             for choice, statements in css:
-                r += "\t"*(level + 1) + _print_expression(ns, choice)[0] + ": begin\n"
+                r += _tab*(level + 1) + _print_expression(ns, choice)[0] + ": begin\n"
                 r += _print_node(ns, at, level + 2, statements, target_filter)
-                r += "\t"*(level + 1) + "end\n"
+                r += _tab*(level + 1) + "end\n"
             if "default" in node.cases:
-                r += "\t"*(level + 1) + "default: begin\n"
+                r += _tab*(level + 1) + "default: begin\n"
                 r += _print_node(ns, at, level + 2, node.cases["default"], target_filter)
-                r += "\t"*(level + 1) + "end\n"
-            r += "\t"*level + "endcase\n"
+                r += _tab*(level + 1) + "end\n"
+            r += _tab*level + "endcase\n"
             return r
         else:
             return ""
@@ -327,11 +329,11 @@ def _print_node(ns, at, level, node, target_filter=None):
                 s += ns.get_name(arg)
             else:
                 s += str(arg)
-        return "\t"*level + "$display(" + s + ");\n"
+        return _tab*level + "$display(" + s + ");\n"
 
     # Finish.
     elif isinstance(node, Finish):
-        return "\t"*level + "$finish;\n"
+        return _tab*level + "$finish;\n"
 
     # Unknown.
     else:
@@ -390,23 +392,23 @@ def _print_module(f, ios, name, ns, attr_translate):
         firstp = False
         attr = _print_attribute(sig.attr, attr_translate)
         if attr:
-            r += "\t" + attr
+            r += _tab + attr
         sig.type = "wire"
         sig.name = ns.get_name(sig)
         sig.port = True
         if sig in inouts:
             sig.direction = "inout"
-            r += "\tinout  wire " + _print_signal(ns, sig)
+            r += _tab + "inout  wire " + _print_signal(ns, sig)
         elif sig in targets:
             sig.direction = "output"
             if sig in wires:
-                r += "\toutput wire " + _print_signal(ns, sig)
+                r += _tab + "output wire " + _print_signal(ns, sig)
             else:
                 sig.type = "reg"
-                r += "\toutput reg  " + _print_signal(ns, sig)
+                r += _tab + "output reg  " + _print_signal(ns, sig)
         else:
             sig.direction = "input"
-            r += "\tinput  wire " + _print_signal(ns, sig)
+            r += _tab + "input  wire " + _print_signal(ns, sig)
     r += "\n);\n\n"
 
     return r
@@ -451,7 +453,7 @@ def _print_combinatorial_logic_sim(f, ns):
                 r += "assign " + _print_node(ns, _AT_BLOCKING, 0, stmts[0])
             else:
                 r += "always @(*) begin\n"
-                r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
+                r += _tab + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
                 r += _print_node(ns, _AT_NONBLOCKING, 1, stmts, t)
                 r += "end\n"
     r += "\n"
@@ -468,7 +470,7 @@ def _print_combinatorial_logic_synth(f, ns):
             else:
                 r += "always @(*) begin\n"
                 for t in g[0]:
-                    r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
+                    r += _tab + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
                 r += _print_node(ns, _AT_NONBLOCKING, 1, g[1])
                 r += "end\n"
     r += "\n"