From 84e7e816c77359a667ffa62c64bf59099845b282 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 5 Sep 2024 10:16:43 +0200 Subject: [PATCH] efinix: pll now force the generated clock into cd.clk *WARNING* --- litex/soc/cores/clock/efinix.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py index 0ca5ebf6e..04a012f88 100644 --- a/litex/soc/cores/clock/efinix.py +++ b/litex/soc/cores/clock/efinix.py @@ -107,11 +107,15 @@ class EFINIXPLL(LiteXModule): clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name if cd is not None: - self.platform.add_extension([(clk_out_name, 0, Pins(1))]) clk_name = f"{cd.name}_clk" + clk_out_name = clk_name # To unify constraints names + self.platform.add_extension([(clk_out_name, 0, Pins(1))]) clk_out = self.platform.request(clk_out_name) self.comb += cd.clk.eq(clk_out) - self.platform.add_period_constraint(clk=clk_out, period=1e9/freq, name=clk_name) + # Efinity will generate xxx.pt.sdc constraints automaticaly, + # so, the user realy need to use the toplevel pin from the pll instead of an intermediate signal + # This is a dirty workaround. But i don't have any better + cd.clk = clk_out if with_reset: self.specials += AsyncResetSynchronizer(cd, ~self.locked) self.platform.toolchain.excluded_ios.append(clk_out_name)