diff --git a/migen/genlib/io.py b/migen/genlib/io.py
index 3439f0883..12d8b0a11 100644
--- a/migen/genlib/io.py
+++ b/migen/genlib/io.py
@@ -48,12 +48,12 @@ class CRG(Module):
             clk = clk_se
 
         # Power on Reset (vendor agnostic)
-        rst = Signal(reset=1)
-        self.sync.por += rst.eq(rst)
+        int_rst = Signal(reset=1)
+        self.sync.por += int_rst.eq(rst)
         self.comb += [
             self.cd_sys.clk.eq(clk),
             self.cd_por.clk.eq(clk),
-            self.cd_sys.rst.eq(rst)
+            self.cd_sys.rst.eq(int_rst)
         ]