Add ASMIprobe core

common/csrbase.h

@@ -7,5 +7,6 @@
 #define TIMER0_BASE	0xe0001800
 #define MINIMAC_BASE	0xe0002000
 #define FB_BASE		0xe0002800
+#define ASMIPROBE_BASE	0xe0003000
 
 #endif /* __CSRBASE_H */

milkymist/asmiprobe/__init__.py

@@ -0,0 +1,36 @@
+from migen.fhdl.structure import *
+from migen.bank.description import *
+from migen.bank import csrgen
+
+class ASMIprobe:
+	def __init__(self, address, hub, trace_depth=16):
+		self.hub = hub
+		self.trace_depth = trace_depth
+		
+		slot_count = len(self.hub.get_slots())
+		assert(self.trace_depth < 256)
+		assert(slot_count < 256)
+		
+		self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+		self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+		self._slot_status = [RegisterField("slot_status", 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+			for i in range(slot_count)]
+		self._trace = [RegisterField("trace", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+			for i in range(self.trace_depth)]
+
+		self.bank = csrgen.Bank([self._slot_count, self._trace_depth]
+			+ self._slot_status + self._trace, address=address)
+	
+	def get_fragment(self):
+		slots = self.hub.get_slots()
+		comb = [
+			self._slot_count.field.w.eq(len(slots)),
+			self._trace_depth.field.w.eq(self.trace_depth)
+		]
+		for slot, status in zip(slots, self._slot_status):
+			comb.append(status.field.w.eq(slot.state))
+		shift_tags = [self._trace[n].field.w.eq(self._trace[n+1].field.w)
+			for n in range(len(self._trace) - 1)]
+		shift_tags.append(self._trace[-1].field.w.eq(self.hub.tag_call))
+		sync = [If(self.hub.call, *shift_tags)]
+		return Fragment(comb, sync) + self.bank.get_fragment()

milkymist/framebuffer/__init__.py

@@ -247,10 +247,11 @@ class Framebuffer:
 			"hres", "hsync_start", "hsync_end", "hscan", 
 			"vres", "vsync_start", "vsync_end", "vscan"])
 		g.add_connection(vtg, fifo)
-		self._comp_actor = CompositeActor(g, debugger=False)
+		self._comp_actor = CompositeActor(g, debugger=True)
 		
 		self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
 			address=address)
+		self._comp_actor.debugger.print_map()
 		
 		# VGA clock input
 		if not simulation:

top.py

@@ -6,7 +6,7 @@ from migen.fhdl import verilog, autofragment
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 
 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
-	identifier, timer, minimac3, framebuffer
+	identifier, timer, minimac3, framebuffer, asmiprobe
 from cmacros import get_macros
 from constraints import Constraints
 
@@ -124,13 +124,15 @@ def get():
 	identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
 	timer0 = timer.Timer(csr_offset("TIMER0"))
 	fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
+	asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
 		uart0.bank.interface,
 		dfii0.bank.interface,
 		identifier0.bank.interface,
 		timer0.bank.interface,
 		minimac0.bank.interface,
-		fb0.bank.interface
+		fb0.bank.interface,
+		asmiprobe0.bank.interface
 	])
 	
 	#