From 85813b3b586313a63bcb1b84ba22a176c3344b6e Mon Sep 17 00:00:00 2001 From: Kenneth Ryerson Date: Mon, 3 Jun 2013 21:52:21 +0200 Subject: [PATCH] csr/sram: fix reads on high addresses when word_bits != 0 --- migen/bus/csr.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/migen/bus/csr.py b/migen/bus/csr.py index fd812e9ab..b0ed1966b 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -107,10 +107,10 @@ class SRAM(Module): ] if self._page is None: - self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)]) + self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)]) else: pv = self._page.storage - self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv)) + self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv)) def get_csrs(self): if self._page is None: