From 85ef3bd8a79a2d5186e923361a3a237d0d507288 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 3 Jan 2024 19:41:03 +0100 Subject: [PATCH] cpu/gowin_emcu: Add missing reset signals. --- litex/soc/cores/cpu/gowin_emcu/core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/gowin_emcu/core.py b/litex/soc/cores/cpu/gowin_emcu/core.py index 5046f01a2..4a9dcdb6f 100644 --- a/litex/soc/cores/cpu/gowin_emcu/core.py +++ b/litex/soc/cores/cpu/gowin_emcu/core.py @@ -63,8 +63,8 @@ class GowinEMCU(CPU): self.cpu_params.update( # Clk/Rst. i_FCLK = ClockSignal("sys"), - i_PORESETN = ~self.reset, - i_SYSRESETN = ~self.reset, + i_PORESETN = ~ResetSignal("sys") & ~self.reset, + i_SYSRESETN = ~ResetSignal("sys") & ~self.reset, i_MTXREMAP = Signal(4, reset=0b1111), o_MTXHRESETN = bus_reset_n, @@ -124,7 +124,7 @@ class GowinEMCU(CPU): i_CEB = ~sram0_wren[i // 2], i_CLKA = ClockSignal("sys"), i_CLKB = ClockSignal("sys"), - i_RESETA = 0, + i_RESETA = ~bus_reset_n, i_RESETB = ~bus_reset_n, i_OCE = 1, i_BLKSELA = Cat(sram0_cs, sram0_cs, sram0_cs),