From 85f892227afc622d30ec73b3f399155dca7b8896 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Sun, 23 Jan 2022 16:34:47 +0100 Subject: [PATCH] cores/cpu/gowin: re-enable write access to csr bus --- litex/soc/cores/cpu/gowin_emcu/core.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/litex/soc/cores/cpu/gowin_emcu/core.py b/litex/soc/cores/cpu/gowin_emcu/core.py index 81afa60a4..c30b50061 100644 --- a/litex/soc/cores/cpu/gowin_emcu/core.py +++ b/litex/soc/cores/cpu/gowin_emcu/core.py @@ -169,9 +169,6 @@ class GowinEMCU(CPU): self.periph_buses = [self.pbus] ahb_targexp0 = ahb.Interface() for s, _ in ahb_targexp0.master_signals: - # TODO: due to unexpected writes by the CPU bus is currently forced read-only - if s == "write": - continue self.cpu_params[f"o_TARGEXP0H{s.upper()}"] = getattr(ahb_targexp0, s) for s, _ in ahb_targexp0.slave_signals: self.cpu_params[f"i_TARGEXP0H{s.upper()}"] = getattr(ahb_targexp0, s)