diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 100ce4be7..08c2c8a26 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -238,7 +238,7 @@ class VexRiscv(CPU, AutoCSR):
     def set_reset_address(self, reset_address):
         assert not hasattr(self, "reset_address")
         self.reset_address = reset_address
-        self.cpu_params.update(i_externalResetVector=reset_address)
+        self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))
 
     def add_timer(self):
         self.submodules.timer = VexRiscvTimer()