From 862e784eaefa41a05d92caa132d73b25205ad74c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Jan 2020 16:20:25 +0100 Subject: [PATCH] cpu/vexriscv: use 32-bit signal for externalResetVector --- litex/soc/cores/cpu/vexriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 100ce4be7..08c2c8a26 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -238,7 +238,7 @@ class VexRiscv(CPU, AutoCSR): def set_reset_address(self, reset_address): assert not hasattr(self, "reset_address") self.reset_address = reset_address - self.cpu_params.update(i_externalResetVector=reset_address) + self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address)) def add_timer(self): self.submodules.timer = VexRiscvTimer()