From 86952a6e06abcaa97e45da3acd020f2e19912694 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 May 2020 18:04:08 +0200 Subject: [PATCH] interconnect/wishbone: remove CSRBank (probably not used by anyone). --- litex/soc/interconnect/wishbone.py | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index b1c1dd219..187f2c313 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -517,28 +517,3 @@ class Cache(Module): ) ) ) - -# Wishbone CSRBank --------------------------------------------------------------------------------- - -class CSRBank(csr.GenericBank): - def __init__(self, description, bus=None): - if bus is None: - bus = Interface() - self.bus = bus - - ### - - csr.GenericBank.__init__(self, description, len(self.bus.dat_w)) - - for i, c in enumerate(self.simple_csrs): - self.comb += [ - c.r.eq(self.bus.dat_w[:c.size]), - c.re.eq(self.bus.cyc & self.bus.stb & ~self.bus.ack & self.bus.we & \ - (self.bus.adr[:self.decode_bits] == i)) - ] - - brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs)) - self.sync += [ - Case(self.bus.adr[:self.decode_bits], brcases), - If(bus.ack, bus.ack.eq(0)).Elif(bus.cyc & bus.stb, bus.ack.eq(1)) - ]