diff --git a/litex/build/parser.py b/litex/build/parser.py
index ca46efe94..31c15308e 100644
--- a/litex/build/parser.py
+++ b/litex/build/parser.py
@@ -9,7 +9,6 @@ import sys
 import logging
 import argparse
 import importlib
-import time
 
 from litex.soc.cores import cpu
 from litex.soc.integration import soc_core
@@ -66,9 +65,6 @@ class LiteXArgumentParser(argparse.ArgumentParser):
             self.set_platform(platform)
             self.add_target_group()
         self.add_logging_group()
-        # workaround for backward compatibility
-        self._rm_jtagbone = False
-        self._rm_uartbone = False
 
     def set_platform(self, platform):
         """ set platform. Check first if not already set
@@ -110,17 +106,13 @@ class LiteXArgumentParser(argparse.ArgumentParser):
         """ wrapper to add argument to "Target options group" from outer of this
         class
         """
-        arg = args[0]
-        if arg in ["--with-jtagbone", "--with-uartbone"]:
-            if arg == "--with-jtagbone":
+        if args[0] in ["--with-jtagbone", "--with-uartbone"]:
+            if args[0] == "--with-jtagbone":
                 self._rm_jtagbone = True
-            else:
+            if args[0] == "--with-uartbone":
                 self._rm_uartbone = True
-            print("Warning {} {} {}".format(
-                colorer(arg, color="red"),
-                colorer(" is added by SoCCore. ", color="red"),
-                colorer("Please remove this option from target", color="yellow")))
-            time.sleep(2)
+            from litex.compat import compat_notice
+            compat_notice(f"Adding {args[0]} in target", date="2023-10-23", info=f"{args[0]} is now directly added by SoCCore, please remove from target.")
             return # bypass insert
         if self._target_group is None:
             self._target_group = self.add_argument_group(title="Target options")
@@ -169,9 +161,9 @@ class LiteXArgumentParser(argparse.ArgumentParser):
         soc_arg = soc_core.soc_core_argdict(self._args) # FIXME: Rename to soc_argdict in the future.
 
         # Work around for backward compatibility
-        if self._rm_jtagbone:
+        if getattr(self, "_rm_jtagbone", False):
             soc_arg.pop("with_jtagbone")
-        if self._rm_uartbone:
+        if getattr(self, "_rm_uartbone", False):
             soc_arg.pop("with_uartbone")
         return soc_arg
 
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 2ed96f46b..668d2a9ca 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1460,6 +1460,15 @@ class LiteXSoC(SoC):
         from litex.soc.cores import uart
         from litex.soc.cores.jtag import JTAGPHY
 
+        # Check if JTAGBone is supported (SPI only device or no user access).
+        if not self.platform.jtag_support:
+            self.logger.error("{} {} on {} device.".format(
+                colorer("JTAGBone"),
+                colorer("not supported", color="red"),
+                colorer(self.platform.device)
+            ))
+            raise SoCError()
+
         # Core.
         self.check_if_exists(name)
         jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain, platform=self.platform)
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 4a9b5e10e..28611d197 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -183,15 +183,10 @@ class SoCCore(LiteXSoC):
 
         # Parameters check validity ----------------------------------------------------------------
 
-        # Check if jtagbone is supported (SPI only device or no user access).
-        if with_jtagbone:
-            if not platform.jtag_support:
-                self.logger.error("{} {} with {} FPGA".format(
-                    colorer("JTAGBone isn't supported for platform", color="red"),
-                    platform.name, platform.device))
-                raise SoCError()
+        # FIXME: Move to soc.py?
+
         if with_uart:
-            # crossover+uartbone is kept as backward compatibility
+            # crossover+uartbone is kept as backward compatibility
             if uart_name == "crossover+uartbone":
                 self.logger.warning("{} UART: is deprecated {}".format(
                     colorer(uart_name, color="yellow"),
@@ -201,9 +196,9 @@ class SoCCore(LiteXSoC):
                 self._uartbone = True
                 uart_name      = "crossover"
 
-            # JTAGBone and jtag_uart can't be used at the same time.
+            # JTAGBone and jtag_uart can't be used at the same time.
             assert not (with_jtagbone and uart_name == "jtag_uart")
-            # UARTBone and serial can't be used at the same time.
+            # UARTBone and serial can't be used at the same time.
             assert not (with_uartbone and uart_name == "serial")
 
         # Modules instances ------------------------------------------------------------------------