diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 805610907..98d45c651 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -25,7 +25,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
-        self.submodules.pll = pll = S7PLL()
+        self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 91df0d384..663eaf0b6 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -24,7 +24,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 10078b300..c2f94e5a9 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -24,7 +24,7 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index fb863e716..72c5e8963 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -23,7 +23,7 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_clk100 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 9ce1719d9..ca485774f 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -26,7 +26,7 @@ class _CRG(Module):
         self.clock_domains.cd_clk200 = ClockDomain()
         self.clock_domains.cd_clk100 = ClockDomain()
 
-        self.submodules.pll = pll = S7MMCM()
+        self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)