diff --git a/README.md b/README.md
index 960f0775b..e90a59f34 100644
--- a/README.md
+++ b/README.md
@@ -48,7 +48,7 @@ http://m-labs.hk/gateware.html
 
 ```python
 from migen.fhdl.std import *
-from mibuild.platforms import m1
+from migen.build.platforms import m1
 plat = m1.Platform()
 led = plat.request("user_led")
 m = Module()
diff --git a/doc/conf.py b/doc/conf.py
index 9bac6059a..fc7f11807 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -90,7 +90,7 @@ exclude_patterns = ['_build']
 pygments_style = 'sphinx'
 
 # A list of ignored prefixes for module index sorting.
-modindex_common_prefix = ['migen.', 'mibuild.']
+modindex_common_prefix = ['migen.']
 
 numpydoc_show_class_members = False
 
diff --git a/mibuild/altera/__init__.py b/mibuild/altera/__init__.py
deleted file mode 100644
index 9a0845803..000000000
--- a/mibuild/altera/__init__.py
+++ /dev/null
@@ -1,2 +0,0 @@
-from mibuild.altera.platform import AlteraPlatform
-from mibuild.altera.programmer import USBBlaster
diff --git a/mibuild/lattice/__init__.py b/mibuild/lattice/__init__.py
deleted file mode 100644
index 02116134a..000000000
--- a/mibuild/lattice/__init__.py
+++ /dev/null
@@ -1,2 +0,0 @@
-from mibuild.lattice.platform import LatticePlatform
-from mibuild.lattice.programmer import LatticeProgrammer
diff --git a/mibuild/sim/__init__.py b/mibuild/sim/__init__.py
deleted file mode 100644
index 439f0a8e1..000000000
--- a/mibuild/sim/__init__.py
+++ /dev/null
@@ -1 +0,0 @@
-from mibuild.sim.platform import SimPlatform
diff --git a/mibuild/xilinx/__init__.py b/mibuild/xilinx/__init__.py
deleted file mode 100644
index 0594435c4..000000000
--- a/mibuild/xilinx/__init__.py
+++ /dev/null
@@ -1,2 +0,0 @@
-from mibuild.xilinx.platform import XilinxPlatform
-from mibuild.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept
diff --git a/mibuild/__init__.py b/migen/build/__init__.py
similarity index 100%
rename from mibuild/__init__.py
rename to migen/build/__init__.py
diff --git a/migen/build/altera/__init__.py b/migen/build/altera/__init__.py
new file mode 100644
index 000000000..9fc45d4a4
--- /dev/null
+++ b/migen/build/altera/__init__.py
@@ -0,0 +1,2 @@
+from migen.build.altera.platform import AlteraPlatform
+from migen.build.altera.programmer import USBBlaster
diff --git a/mibuild/altera/common.py b/migen/build/altera/common.py
similarity index 100%
rename from mibuild/altera/common.py
rename to migen/build/altera/common.py
diff --git a/mibuild/altera/platform.py b/migen/build/altera/platform.py
similarity index 89%
rename from mibuild/altera/platform.py
rename to migen/build/altera/platform.py
index 1cbf2a193..43841fa7b 100644
--- a/mibuild/altera/platform.py
+++ b/migen/build/altera/platform.py
@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.altera import common, quartus
+from migen.build.generic_platform import GenericPlatform
+from migen.build.altera import common, quartus
 
 
 class AlteraPlatform(GenericPlatform):
diff --git a/mibuild/altera/programmer.py b/migen/build/altera/programmer.py
similarity index 85%
rename from mibuild/altera/programmer.py
rename to migen/build/altera/programmer.py
index 77a24cc0d..369f7db1b 100644
--- a/mibuild/altera/programmer.py
+++ b/migen/build/altera/programmer.py
@@ -1,6 +1,6 @@
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
+from migen.build.generic_programmer import GenericProgrammer
 
 
 class USBBlaster(GenericProgrammer):
diff --git a/mibuild/altera/quartus.py b/migen/build/altera/quartus.py
similarity index 97%
rename from mibuild/altera/quartus.py
rename to migen/build/altera/quartus.py
index ad5f50b1b..aab2048b8 100644
--- a/mibuild/altera/quartus.py
+++ b/migen/build/altera/quartus.py
@@ -5,9 +5,9 @@ import os
 import subprocess
 
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import (Pins, IOStandard, Misc)
 
-from mibuild import tools
+from migen.build.generic_platform import Pins, IOStandard, Misc
+from migen.build import tools
 
 
 def _format_constraint(c, signame, fmt_r):
@@ -92,7 +92,7 @@ def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
 
 
 def _run_quartus(build_name, quartus_path):
-    build_script_contents = """# Autogenerated by mibuild
+    build_script_contents = """# Autogenerated by Migen
 
 quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
 quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
diff --git a/mibuild/fpgalink_programmer.py b/migen/build/fpgalink_programmer.py
similarity index 96%
rename from mibuild/fpgalink_programmer.py
rename to migen/build/fpgalink_programmer.py
index c711b0ce7..fc7586dce 100644
--- a/mibuild/fpgalink_programmer.py
+++ b/migen/build/fpgalink_programmer.py
@@ -1,7 +1,7 @@
 import os
 
-from mibuild.generic_programmer import GenericProgrammer
-from mibuild.xilinx.programmer import _create_xsvf
+from migen.build.generic_programmer import GenericProgrammer
+from migen.build.xilinx.programmer import _create_xsvf
 
 try:
    import fl
diff --git a/mibuild/generic_platform.py b/migen/build/generic_platform.py
similarity index 99%
rename from mibuild/generic_platform.py
rename to migen/build/generic_platform.py
index 04d4b3b4a..ff8a51e34 100644
--- a/mibuild/generic_platform.py
+++ b/migen/build/generic_platform.py
@@ -7,7 +7,7 @@ from migen.genlib.io import CRG
 from migen.fhdl import verilog, edif
 from migen.util.misc import autotype
 
-from mibuild import tools
+from migen.build import tools
 
 
 class ConstraintError(Exception):
diff --git a/mibuild/generic_programmer.py b/migen/build/generic_programmer.py
similarity index 100%
rename from mibuild/generic_programmer.py
rename to migen/build/generic_programmer.py
diff --git a/migen/build/lattice/__init__.py b/migen/build/lattice/__init__.py
new file mode 100644
index 000000000..78b2035df
--- /dev/null
+++ b/migen/build/lattice/__init__.py
@@ -0,0 +1,2 @@
+from migen.build.lattice.platform import LatticePlatform
+from migen.build.lattice.programmer import LatticeProgrammer
diff --git a/mibuild/lattice/common.py b/migen/build/lattice/common.py
similarity index 100%
rename from mibuild/lattice/common.py
rename to migen/build/lattice/common.py
diff --git a/mibuild/lattice/diamond.py b/migen/build/lattice/diamond.py
similarity index 95%
rename from mibuild/lattice/diamond.py
rename to migen/build/lattice/diamond.py
index 0b9f486cc..098c67deb 100644
--- a/mibuild/lattice/diamond.py
+++ b/migen/build/lattice/diamond.py
@@ -6,10 +6,10 @@ import subprocess
 import shutil
 
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import *
 
-from mibuild import tools
-from mibuild.lattice import common
+from migen.build.generic_platform import *
+from migen.build import tools
+from migen.build.lattice import common
 
 
 def _format_constraint(c):
@@ -60,7 +60,7 @@ def _build_files(device, sources, vincpaths, build_name):
 
 def _run_diamond(build_name, source, ver=None):
     if sys.platform == "win32" or sys.platform == "cygwin":
-        build_script_contents = "REM Autogenerated by mibuild\n"
+        build_script_contents = "REM Autogenerated by Migen\n"
         build_script_contents = "pnmainc " + build_name + ".tcl\n"
         build_script_file = "build_" + build_name + ".bat"
         tools.write_to_file(build_script_file, build_script_contents)
diff --git a/mibuild/lattice/platform.py b/migen/build/lattice/platform.py
similarity index 89%
rename from mibuild/lattice/platform.py
rename to migen/build/lattice/platform.py
index 08be54e99..73742231d 100644
--- a/mibuild/lattice/platform.py
+++ b/migen/build/lattice/platform.py
@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.lattice import common, diamond
+from migen.build.generic_platform import GenericPlatform
+from migen.build.lattice import common, diamond
 
 
 class LatticePlatform(GenericPlatform):
diff --git a/mibuild/lattice/programmer.py b/migen/build/lattice/programmer.py
similarity index 94%
rename from mibuild/lattice/programmer.py
rename to migen/build/lattice/programmer.py
index fc8664968..cc3c50bd0 100644
--- a/mibuild/lattice/programmer.py
+++ b/migen/build/lattice/programmer.py
@@ -1,8 +1,9 @@
 import os
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
-from mibuild import tools
+from migen.build.generic_programmer import GenericProgrammer
+from migen.build import tools
+
 
 # XXX Lattice programmer need an .xcf file, will need clean up and support for more parameters
 _xcf_template = """
diff --git a/mibuild/openocd.py b/migen/build/openocd.py
similarity index 93%
rename from mibuild/openocd.py
rename to migen/build/openocd.py
index 47e51c7e5..aec29980f 100644
--- a/mibuild/openocd.py
+++ b/migen/build/openocd.py
@@ -1,6 +1,6 @@
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
+from migen.build.generic_programmer import GenericProgrammer
 
 
 class OpenOCD(GenericProgrammer):
diff --git a/mibuild/platforms/__init__.py b/migen/build/platforms/__init__.py
similarity index 100%
rename from mibuild/platforms/__init__.py
rename to migen/build/platforms/__init__.py
diff --git a/mibuild/platforms/apf27.py b/migen/build/platforms/apf27.py
similarity index 98%
rename from mibuild/platforms/apf27.py
rename to migen/build/platforms/apf27.py
index ee21f7921..ea182e21c 100644
--- a/mibuild/platforms/apf27.py
+++ b/migen/build/platforms/apf27.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _ios = [
     ("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")),
diff --git a/mibuild/platforms/apf51.py b/migen/build/platforms/apf51.py
similarity index 98%
rename from mibuild/platforms/apf51.py
rename to migen/build/platforms/apf51.py
index 4cfaa9d82..f776cdaca 100644
--- a/mibuild/platforms/apf51.py
+++ b/migen/build/platforms/apf51.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _ios = [
     ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")),
diff --git a/mibuild/platforms/de0nano.py b/migen/build/platforms/de0nano.py
similarity index 95%
rename from mibuild/platforms/de0nano.py
rename to migen/build/platforms/de0nano.py
index 7e6d47b20..4ef34dafd 100644
--- a/mibuild/platforms/de0nano.py
+++ b/migen/build/platforms/de0nano.py
@@ -1,9 +1,10 @@
 # This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.altera import AlteraPlatform
-from mibuild.altera.programmer import USBBlaster
+from migen.build.generic_platform import *
+from migen.build.altera import AlteraPlatform
+from migen.build.altera.programmer import USBBlaster
+
 
 _io = [
     ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
diff --git a/mibuild/platforms/kc705.py b/migen/build/platforms/kc705.py
similarity index 98%
rename from mibuild/platforms/kc705.py
rename to migen/build/platforms/kc705.py
index bc67d2bec..eb51ab332 100644
--- a/mibuild/platforms/kc705.py
+++ b/migen/build/platforms/kc705.py
@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
-from mibuild.xilinx.ise import XilinxISEToolchain
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer, iMPACT
+from migen.build.xilinx.ise import XilinxISEToolchain
+
 
 _io = [
     ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
diff --git a/mibuild/platforms/lx9_microboard.py b/migen/build/platforms/lx9_microboard.py
similarity index 98%
rename from mibuild/platforms/lx9_microboard.py
rename to migen/build/platforms/lx9_microboard.py
index ea0cb4159..fb13b1cb8 100644
--- a/mibuild/platforms/lx9_microboard.py
+++ b/migen/build/platforms/lx9_microboard.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
         ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),
diff --git a/mibuild/platforms/m1.py b/migen/build/platforms/m1.py
similarity index 97%
rename from mibuild/platforms/m1.py
rename to migen/build/platforms/m1.py
index 01b9e866e..65216c881 100644
--- a/mibuild/platforms/m1.py
+++ b/migen/build/platforms/m1.py
@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import UrJTAG
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import UrJTAG
+
 
 _io = [
     ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
diff --git a/mibuild/platforms/mercury.py b/migen/build/platforms/mercury.py
similarity index 96%
rename from mibuild/platforms/mercury.py
rename to migen/build/platforms/mercury.py
index 77a884bab..699218dff 100644
--- a/mibuild/platforms/mercury.py
+++ b/migen/build/platforms/mercury.py
@@ -1,9 +1,9 @@
 # This file is Copyright (c) 2015 William D. Jones <thor0505@comcast.net>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg
 
 
 _io = [
@@ -71,7 +71,7 @@ _connectors = [
 ]
 
 # Some default useful extensions- use platform.add_extension() to use, e.g.
-# from mibuild.platforms import mercury
+# from migen.build.platforms import mercury
 # plat = mercury.Platform()
 # plat.add_extension(mercury.gpio_sram)
 
diff --git a/mibuild/platforms/mimasv2.py b/migen/build/platforms/mimasv2.py
similarity index 98%
rename from mibuild/platforms/mimasv2.py
rename to migen/build/platforms/mimasv2.py
index fd8465692..703fdc49b 100644
--- a/mibuild/platforms/mimasv2.py
+++ b/migen/build/platforms/mimasv2.py
@@ -1,5 +1,5 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
 
 
 _io = [
diff --git a/mibuild/platforms/minispartan6.py b/migen/build/platforms/minispartan6.py
similarity index 96%
rename from mibuild/platforms/minispartan6.py
rename to migen/build/platforms/minispartan6.py
index 843fa3d5d..c46fa29c2 100644
--- a/mibuild/platforms/minispartan6.py
+++ b/migen/build/platforms/minispartan6.py
@@ -1,9 +1,10 @@
 # This file is Copyright (c) 2015 Matt O'Gorman <mog@rldn.net>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg, FpgaProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg, FpgaProg
+
 
 _io = [
     ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),
diff --git a/mibuild/platforms/mixxeo.py b/migen/build/platforms/mixxeo.py
similarity index 98%
rename from mibuild/platforms/mixxeo.py
rename to migen/build/platforms/mixxeo.py
index 69096e546..8d4c85d83 100644
--- a/mibuild/platforms/mixxeo.py
+++ b/migen/build/platforms/mixxeo.py
@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import UrJTAG
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import UrJTAG
+
 
 _io = [
     ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
diff --git a/mibuild/platforms/ml605.py b/migen/build/platforms/ml605.py
similarity index 95%
rename from mibuild/platforms/ml605.py
rename to migen/build/platforms/ml605.py
index 26ac49fc8..04184b74b 100644
--- a/mibuild/platforms/ml605.py
+++ b/migen/build/platforms/ml605.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
     # System clock (Differential 200MHz)
diff --git a/mibuild/platforms/papilio_pro.py b/migen/build/platforms/papilio_pro.py
similarity index 93%
rename from mibuild/platforms/papilio_pro.py
rename to migen/build/platforms/papilio_pro.py
index 5d35c7a33..8ee330053 100644
--- a/mibuild/platforms/papilio_pro.py
+++ b/migen/build/platforms/papilio_pro.py
@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg
+
 
 _io = [
     ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
diff --git a/mibuild/platforms/pipistrello.py b/migen/build/platforms/pipistrello.py
similarity index 97%
rename from mibuild/platforms/pipistrello.py
rename to migen/build/platforms/pipistrello.py
index 072bcf201..c202556a8 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/migen/build/platforms/pipistrello.py
@@ -1,6 +1,7 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+from migen.build.xilinx.programmer import XC3SProg
+
 
 _io = [
     ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")),  # green at hdmi
diff --git a/mibuild/platforms/rhino.py b/migen/build/platforms/rhino.py
similarity index 98%
rename from mibuild/platforms/rhino.py
rename to migen/build/platforms/rhino.py
index 5f766ff94..0cb995960 100644
--- a/mibuild/platforms/rhino.py
+++ b/migen/build/platforms/rhino.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
     ("user_led", 0, Pins("Y3")),
diff --git a/mibuild/platforms/roach.py b/migen/build/platforms/roach.py
similarity index 93%
rename from mibuild/platforms/roach.py
rename to migen/build/platforms/roach.py
index 66f813376..19c1ccb4a 100644
--- a/mibuild/platforms/roach.py
+++ b/migen/build/platforms/roach.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
     ("epb", 0,
diff --git a/mibuild/platforms/sim.py b/migen/build/platforms/sim.py
similarity index 92%
rename from mibuild/platforms/sim.py
rename to migen/build/platforms/sim.py
index 55dec4675..0e4a40d1b 100644
--- a/mibuild/platforms/sim.py
+++ b/migen/build/platforms/sim.py
@@ -1,5 +1,5 @@
-from mibuild.generic_platform import *
-from mibuild.sim import SimPlatform
+from migen.build.generic_platform import *
+from migen.build.sim import SimPlatform
 
 
 class SimPins(Pins):
diff --git a/mibuild/platforms/usrp_b100.py b/migen/build/platforms/usrp_b100.py
similarity index 98%
rename from mibuild/platforms/usrp_b100.py
rename to migen/build/platforms/usrp_b100.py
index 6448a6ccf..2e1627382 100644
--- a/mibuild/platforms/usrp_b100.py
+++ b/migen/build/platforms/usrp_b100.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
         ("clk64", 0,
diff --git a/mibuild/platforms/versa.py b/migen/build/platforms/versa.py
similarity index 95%
rename from mibuild/platforms/versa.py
rename to migen/build/platforms/versa.py
index e164bdec4..dc8dd53d1 100644
--- a/mibuild/platforms/versa.py
+++ b/migen/build/platforms/versa.py
@@ -1,9 +1,10 @@
 # This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
-from mibuild.generic_platform import *
-from mibuild.lattice import LatticePlatform
-from mibuild.lattice.programmer import LatticeProgrammer
+from migen.build.generic_platform import *
+from migen.build.lattice import LatticePlatform
+from migen.build.lattice.programmer import LatticeProgrammer
+
 
 _io = [
     ("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
diff --git a/mibuild/platforms/zedboard.py b/migen/build/platforms/zedboard.py
similarity index 98%
rename from mibuild/platforms/zedboard.py
rename to migen/build/platforms/zedboard.py
index 72a799aab..b5d3dcc29 100644
--- a/mibuild/platforms/zedboard.py
+++ b/migen/build/platforms/zedboard.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 # Bank 34 and 35 voltage depend on J18 jumper setting
 _io = [
diff --git a/mibuild/platforms/ztex_115d.py b/migen/build/platforms/ztex_115d.py
similarity index 98%
rename from mibuild/platforms/ztex_115d.py
rename to migen/build/platforms/ztex_115d.py
index 238d64ddf..253a121c9 100644
--- a/mibuild/platforms/ztex_115d.py
+++ b/migen/build/platforms/ztex_115d.py
@@ -1,5 +1,6 @@
-from mibuild.generic_platform import *
-from mibuild.xilinx import XilinxPlatform
+from migen.build.generic_platform import *
+from migen.build.xilinx import XilinxPlatform
+
 
 _io = [
         ("clk_fx", 0, Pins("L22"), IOStandard("LVCMOS33")),
diff --git a/migen/build/sim/__init__.py b/migen/build/sim/__init__.py
new file mode 100644
index 000000000..adbba1c40
--- /dev/null
+++ b/migen/build/sim/__init__.py
@@ -0,0 +1 @@
+from migen.build.sim.platform import SimPlatform
diff --git a/mibuild/sim/common.py b/migen/build/sim/common.py
similarity index 100%
rename from mibuild/sim/common.py
rename to migen/build/sim/common.py
diff --git a/mibuild/sim/dut_tb.cpp b/migen/build/sim/dut_tb.cpp
similarity index 100%
rename from mibuild/sim/dut_tb.cpp
rename to migen/build/sim/dut_tb.cpp
diff --git a/mibuild/sim/platform.py b/migen/build/sim/platform.py
similarity index 86%
rename from mibuild/sim/platform.py
rename to migen/build/sim/platform.py
index c36cef04d..0c5e17d2e 100644
--- a/mibuild/sim/platform.py
+++ b/migen/build/sim/platform.py
@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.sim import common, verilator
+from migen.build.generic_platform import GenericPlatform
+from migen.build.sim import common, verilator
 
 
 class SimPlatform(GenericPlatform):
diff --git a/mibuild/sim/verilator.py b/migen/build/sim/verilator.py
similarity index 95%
rename from mibuild/sim/verilator.py
rename to migen/build/sim/verilator.py
index 1bc687911..fd1d8be9d 100644
--- a/mibuild/sim/verilator.py
+++ b/migen/build/sim/verilator.py
@@ -6,10 +6,10 @@ import subprocess
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import *
 
-from mibuild import tools
-from mibuild.sim import common
+from migen.build import tools
+from migen.build.generic_platform import *
+from migen.build.sim import common
 
 
 def _build_tb(platform, vns, serial, template):
@@ -90,7 +90,7 @@ def _build_sim(platform, vns, build_name, include_paths, sim_path, serial, verbo
     for path in include_paths:
         include += "-I"+path+" "
 
-    build_script_contents = """# Autogenerated by mibuild
+    build_script_contents = """# Autogenerated by Migen
     rm -rf obj_dir/
 verilator {disable_warnings} -O3 --cc dut.v --exe dut_tb.cpp -LDFLAGS "-lpthread" -trace {include}
 make -j -C obj_dir/ -f Vdut.mk Vdut
@@ -123,7 +123,7 @@ def _run_sim(build_name):
 class SimVerilatorToolchain:
     # XXX fir sim_path
     def build(self, platform, fragment, build_dir="build", build_name="top",
-            sim_path="../migen/mibuild/sim/", serial="console",
+            sim_path="../migen/migen/build/sim/", serial="console",
             run=True, verbose=False):
         tools.mkdir_noerror(build_dir)
         os.chdir(build_dir)
diff --git a/mibuild/tools.py b/migen/build/tools.py
similarity index 100%
rename from mibuild/tools.py
rename to migen/build/tools.py
diff --git a/migen/build/xilinx/__init__.py b/migen/build/xilinx/__init__.py
new file mode 100644
index 000000000..4120abb85
--- /dev/null
+++ b/migen/build/xilinx/__init__.py
@@ -0,0 +1,2 @@
+from migen.build.xilinx.platform import XilinxPlatform
+from migen.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept
diff --git a/mibuild/xilinx/common.py b/migen/build/xilinx/common.py
similarity index 99%
rename from mibuild/xilinx/common.py
rename to migen/build/xilinx/common.py
index ba125659d..7c753ab69 100644
--- a/mibuild/xilinx/common.py
+++ b/migen/build/xilinx/common.py
@@ -7,7 +7,8 @@ from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.io import *
-from mibuild import tools
+
+from migen.build import tools
 
 
 def settings(path, ver=None, sub=None):
diff --git a/mibuild/xilinx/ise.py b/migen/build/xilinx/ise.py
similarity index 97%
rename from mibuild/xilinx/ise.py
rename to migen/build/xilinx/ise.py
index 92f37517d..198960382 100644
--- a/mibuild/xilinx/ise.py
+++ b/migen/build/xilinx/ise.py
@@ -5,9 +5,9 @@ import sys
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 
-from mibuild.generic_platform import *
-from mibuild import tools
-from mibuild.xilinx import common
+from migen.build.generic_platform import *
+from migen.build import tools
+from migen.build.xilinx import common
 
 
 def _format_constraint(c):
@@ -89,12 +89,12 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
         source_cmd = "call "
         script_ext = ".bat"
         shell = ["cmd", "/c"]
-        build_script_contents = "@echo off\nrem Autogenerated by mibuild\n"
+        build_script_contents = "@echo off\nrem Autogenerated by Migen\n"
     else:
         source_cmd = "source "
         script_ext = ".sh"
         shell = ["bash"]
-        build_script_contents = "# Autogenerated by mibuild\nset -e\n"
+        build_script_contents = "# Autogenerated by Migen\nset -e\n"
     if source:
         settings = common.settings(ise_path, ver, "ISE_DS")
         build_script_contents += source_cmd + settings + "\n"
diff --git a/mibuild/xilinx/platform.py b/migen/build/xilinx/platform.py
similarity index 91%
rename from mibuild/xilinx/platform.py
rename to migen/build/xilinx/platform.py
index 201ad53aa..c5422282d 100644
--- a/mibuild/xilinx/platform.py
+++ b/migen/build/xilinx/platform.py
@@ -1,5 +1,5 @@
-from mibuild.generic_platform import GenericPlatform
-from mibuild.xilinx import common, vivado, ise
+from migen.build.generic_platform import GenericPlatform
+from migen.build.xilinx import common, vivado, ise
 
 
 class XilinxPlatform(GenericPlatform):
diff --git a/mibuild/xilinx/programmer.py b/migen/build/xilinx/programmer.py
similarity index 98%
rename from mibuild/xilinx/programmer.py
rename to migen/build/xilinx/programmer.py
index ce7ca8a5a..644c9f7d8 100644
--- a/mibuild/xilinx/programmer.py
+++ b/migen/build/xilinx/programmer.py
@@ -2,8 +2,8 @@ import os
 import sys
 import subprocess
 
-from mibuild.generic_programmer import GenericProgrammer
-from mibuild.xilinx import common
+from migen.build.generic_programmer import GenericProgrammer
+from migen.build.xilinx import common
 
 
 def _run_urjtag(cmds):
diff --git a/mibuild/xilinx/vivado.py b/migen/build/xilinx/vivado.py
similarity index 95%
rename from mibuild/xilinx/vivado.py
rename to migen/build/xilinx/vivado.py
index 8f732a498..8d85885f4 100644
--- a/mibuild/xilinx/vivado.py
+++ b/migen/build/xilinx/vivado.py
@@ -7,10 +7,10 @@ import sys
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-from mibuild.generic_platform import *
 
-from mibuild import tools
-from mibuild.xilinx import common
+from migen.build.generic_platform import *
+from migen.build import tools
+from migen.build.xilinx import common
 
 
 def _format_constraint(c):
@@ -54,13 +54,13 @@ def _build_xdc(named_sc, named_pc):
 
 def _run_vivado(build_name, vivado_path, source, ver=None):
     if sys.platform == "win32" or sys.platform == "cygwin":
-        build_script_contents = "REM Autogenerated by mibuild\n"
+        build_script_contents = "REM Autogenerated by Migen\n"
         build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"
         build_script_file = "build_" + build_name + ".bat"
         tools.write_to_file(build_script_file, build_script_contents)
         r = subprocess.call([build_script_file])
     else:
-        build_script_contents = "# Autogenerated by mibuild\nset -e\n"
+        build_script_contents = "# Autogenerated by Migen\nset -e\n"
         settings = common.settings(vivado_path, ver)
         build_script_contents += "source " + settings + "\n"
         build_script_contents += "vivado -mode batch -source " + build_name + ".tcl\n"