From 87336128a3769d278b6c0fe29520e5785e5cf03b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 26 Feb 2013 23:25:10 +0100
Subject: [PATCH] sim: update

---
 sim/tb_RecorderCsr.py                | 6 +-----
 sim/tb_TriggerCsr.py                 | 8 ++------
 sim/{tb_migcope.py => tb_miscope.py} | 9 +++------
 sim/{tb_spi2Csr.py => tb_spi2csr.py} | 6 ++----
 4 files changed, 8 insertions(+), 21 deletions(-)
 rename sim/{tb_migcope.py => tb_miscope.py} (96%)
 rename sim/{tb_spi2Csr.py => tb_spi2csr.py} (98%)

diff --git a/sim/tb_RecorderCsr.py b/sim/tb_RecorderCsr.py
index e36d78448..45e2ea08f 100644
--- a/sim/tb_RecorderCsr.py
+++ b/sim/tb_RecorderCsr.py
@@ -5,11 +5,7 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
 from migen.sim.icarus import Runner
 from migen.bus.transactions import *
 
-import sys
-sys.path.append("../")
-
-from migScope import recorder
-
+from miscope import recorder
 
 arm_done = False
 trig_dat = 0
diff --git a/sim/tb_TriggerCsr.py b/sim/tb_TriggerCsr.py
index eb2f8d1d4..f3db1bdae 100644
--- a/sim/tb_TriggerCsr.py
+++ b/sim/tb_TriggerCsr.py
@@ -5,12 +5,8 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
 from migen.sim.icarus import Runner
 from migen.bus.transactions import *
 
-import sys
-sys.path.append("../")
-
-from migScope import trigger
-
-from migScope.tools.truthtable import *
+from miscope import trigger
+from miscope.tools.truthtable import *
 
 def term_prog(off, dat):
 	for i in range(4):
diff --git a/sim/tb_migcope.py b/sim/tb_miscope.py
similarity index 96%
rename from sim/tb_migcope.py
rename to sim/tb_miscope.py
index b27d4c61a..e44ddc536 100644
--- a/sim/tb_migcope.py
+++ b/sim/tb_miscope.py
@@ -5,12 +5,9 @@ from migen.sim.generic import Simulator, PureSimulable, TopLevel
 from migen.sim.icarus import Runner
 from migen.bus.transactions import *
 
-import sys
-sys.path.append("../")
-
-from migScope import trigger, recorder
-from migScope.tools.truthtable import *
-from migScope.tools.vcd import *
+from miscope import trigger, recorder
+from miscope.tools.truthtable import *
+from miscope.tools.vcd import *
 
 TRIGGER_ADDR  = 0x0000
 RECORDER_ADDR = 0x0200
diff --git a/sim/tb_spi2Csr.py b/sim/tb_spi2csr.py
similarity index 98%
rename from sim/tb_spi2Csr.py
rename to sim/tb_spi2csr.py
index ef3b2d6b2..ecc58e456 100644
--- a/sim/tb_spi2Csr.py
+++ b/sim/tb_spi2csr.py
@@ -7,9 +7,7 @@ from migen.bus.transactions import *
 from migen.bank import description, csrgen
 from migen.bank.description import *
 
-import sys
-sys.path.append("../")
-import spi2Csr
+import miscope.bridges.spi2csr
 
 def get_bit(dat, bit):
 	return int(dat & (1<<bit) != 0)
@@ -144,7 +142,7 @@ def main():
 	bank0 = csrgen.Bank(regs,address=0x0000)
 	
 	# Spi2Csr
-	spi2csr0 = spi2Csr.Spi2Csr(16,8)
+	spi2csr0 = spi2csr.Spi2Csr(16,8)
 	
 	
 	# Csr Interconnect