From 875f34f8e278b73bed5926ee781f87abcc41b255 Mon Sep 17 00:00:00 2001 From: David Lattimore Date: Wed, 6 Jan 2021 09:45:08 +1100 Subject: [PATCH] Lattice NX: Allow up to 320KB of RAM --- litex/soc/cores/ram/lattice_nx.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/ram/lattice_nx.py b/litex/soc/cores/ram/lattice_nx.py index 99de35d1b..52f77a12c 100644 --- a/litex/soc/cores/ram/lattice_nx.py +++ b/litex/soc/cores/ram/lattice_nx.py @@ -26,13 +26,12 @@ class NXLRAM(Module): self.bus = wishbone.Interface(width) assert width in [32, 64] - # TODO: allow larger sizes to support Crosslink/NX-17 & Certus if width == 32: - assert size in [64*kB, 128*kB] + assert size in [64*kB, 128*kB, 192*kB, 256*kB, 320*kB] depth_cascading = size//(64*kB) width_cascading = 1 if width == 64: - assert size in [128*kB] + assert size in [128*kB, 256*kB] depth_cascading = size//(128*kB) width_cascading = 2 @@ -46,7 +45,7 @@ class NXLRAM(Module): wren = Signal() self.comb += [ datain.eq(self.bus.dat_w[32*w:32*(w+1)]), - If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d, + If(self.bus.adr[14:14+depth_cascading.bit_length()] == d, cs.eq(1), wren.eq(self.bus.we & self.bus.stb & self.bus.cyc), self.bus.dat_r[32*w:32*(w+1)].eq(dataout)