diff --git a/litex/compat/soc_core.py b/litex/compat/soc_core.py index 1cb7da0ef..31de6c722 100644 --- a/litex/compat/soc_core.py +++ b/litex/compat/soc_core.py @@ -75,8 +75,7 @@ class SoCCoreCompat: # Finalization --------------------------------------------------------------------------------- - def do_finalize(self): - # Retro-compatibility + def finalize_wb_slaves(self): for address, interface in self.wb_slaves.items(): wb_name = None for name, region in self.bus.regions.items(): @@ -84,8 +83,8 @@ class SoCCoreCompat: wb_name = name break self.bus.add_slave(name=wb_name, slave=interface) - SoC.do_finalize(self) - # Retro-compatibility + + def finalize_csr_regions(self): for region in self.bus.regions.values(): region.length = region.size region.type = "cached" if region.cached else "io" diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index ddbd85927..cb6f5733e 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -20,6 +20,8 @@ from litex.gen import colorer from litex.gen import LiteXModule from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer +from litex.compat.soc_core import * + from litex.soc.cores import cpu from litex.soc.interconnect.csr import * @@ -809,7 +811,7 @@ class SoCController(LiteXModule): # SoC ---------------------------------------------------------------------------------------------- -class SoC(LiteXModule): +class SoC(LiteXModule, SoCCoreCompat): mem_map = {} def __init__(self, platform, sys_clk_freq, bus_standard = "wishbone", @@ -1147,6 +1149,8 @@ class SoC(LiteXModule): def finalize(self): if self.finalized: return + # Compat ----------------------------------------------------------------------------------- + SoCCoreCompat.finalize_wb_slaves(self) # FIXME: Deprecate compat and remove. # SoC Reset -------------------------------------------------------------------------------- # Connect soc_rst to CRG's rst if present. @@ -1277,6 +1281,9 @@ class SoC(LiteXModule): # Finalize submodules ---------------------------------------------------------------------- Module.finalize(self) + # Compat ----------------------------------------------------------------------------------- + SoCCoreCompat.finalize_csr_regions(self) # FIXME: Deprecate compat and remove. + # SoC Hierarchy ---------------------------------------------------------------------------- self.logger.info(colorer("-"*80, color="bright")) self.logger.info(colorer("SoC Hierarchy:")) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index c9a558724..dc6ae7272 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -41,7 +41,7 @@ __all__ = [ # SoCCore ------------------------------------------------------------------------------------------ -class SoCCore(LiteXSoC, SoCCoreCompat): +class SoCCore(LiteXSoC): # Default register/interrupt/memory mappings (can be redefined by user) csr_map = {} interrupt_map = {} @@ -247,9 +247,6 @@ class SoCCore(LiteXSoC, SoCCoreCompat): def add_csr_region(self, name, origin, busword, obj): self.csr_regions[name] = SoCCSRRegion(origin, busword, obj) - def do_finalize(self): - SoCCoreCompat.do_finalize(self) - # SoCCore arguments -------------------------------------------------------------------------------- def soc_core_args(parser):