From 879f1b38bca3a209cd73c187749490d1e3a592aa Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 3 Nov 2022 20:22:15 +0800 Subject: [PATCH] integration/soc/add_sdram: connect to main bus with its data width Currently we create a 32-bit Wishbone bus, connect LiteDRAM to it and then connect it to the main SoC bus. This prevents us from getting optimized performance from a wider main bus. Make the intermediate bus to have the same width with the main bus. Signed-off-by: Icenowy Zheng --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 65dbbdd3e..e01fba996 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1581,7 +1581,7 @@ class LiteXSoC(SoC): port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2. # Create Wishbone Slave. - wb_sdram = wishbone.Interface() + wb_sdram = wishbone.Interface(data_width=self.bus.data_width) self.bus.add_slave("main_ram", wb_sdram) # L2 Cache