From 8656ea9b67393f6c6350d152658c46e302579256 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Mon, 20 Jul 2020 18:23:09 +0200 Subject: [PATCH] interconnect/csr_bus: fix paged access warning --- litex/soc/interconnect/csr_bus.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py index b91a458ed..cded5ae29 100644 --- a/litex/soc/interconnect/csr_bus.py +++ b/litex/soc/interconnect/csr_bus.py @@ -100,7 +100,7 @@ class SRAM(Module): page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False) if page_bits: self._page = CSRStorage(page_bits, name=mem.name_override + "_page") - printf("WARNING: SRAM CSR memory will requires paged access.") + print("WARNING: SRAM CSR memory will require paged access.") else: self._page = None if read_only is None: