From 8831acba658087e6558a68037736ed8db9af5e04 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 25 Apr 2024 16:01:49 +0200 Subject: [PATCH] naxriscv fix simulation reset --- litex/soc/cores/cpu/naxriscv/core.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index f79967f03..f4e148ef7 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -452,7 +452,10 @@ class NaxRiscv(CPU): # Reset SoC's CRG when debug_ndmreset rising edge. self.sync.debug_por += debug_ndmreset_last.eq(debug_ndmreset) self.comb += debug_ndmreset_rise.eq(debug_ndmreset & ~debug_ndmreset_last) - self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1)) + if soc.get_build_name() == "sim": + self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1)) + else: + self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1)) self.soc_bus = soc.bus # FIXME: Save SoC Bus instance to retrieve the final mem layout on finalization.