From 88453716dc8aa27cc1f47924283bf45ae6efbda9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Jan 2023 12:59:14 +0100 Subject: [PATCH] cpu/vexriscv_smp/core: Only raise error with FPU. --- litex/soc/cores/cpu/vexriscv_smp/core.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index b42a734bc..ed63ef603 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -487,8 +487,10 @@ class VexRiscvSMP(CPU): # When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus. if len(self.memory_buses) == 0: - if not VexRiscvSMP.wishbone_memory: + if VexRiscvSMP.with_fpu and not VexRiscvSMP.wishbone_memory: raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory to your build command.") + else: + VexRiscvSMP.wishbone_memory = True # Generate cluster name. VexRiscvSMP.generate_cluster_name()