From 885d5b9cb139a842a45a7341f59f7e3bae3237c7 Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Mon, 13 Nov 2023 11:13:19 +1100
Subject: [PATCH] tools/litex_sim: update hybrid etherbone integration

---
 litex/tools/litex_sim.py | 29 ++++-------------------------
 1 file changed, 4 insertions(+), 25 deletions(-)

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 81699f32c..c51595bca 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -233,29 +233,16 @@ class SimSoC(SoCCore):
             else:
                 raise ValueError("Unknown Ethernet PHY model:", ethernet_phy_model)
 
-        # Ethernet and Etherbone -------------------------------------------------------------------
-        if with_ethernet and with_etherbone:
-            # Etherbone.
+        # Etherbone with optional Ethernet ---------------------------------------------------------
+        if with_etherbone:
             self.add_etherbone(
                 phy         = self.ethphy,
                 ip_address  = etherbone_ip_address,
                 mac_address = etherbone_mac_address,
                 data_width  = 8,
-                interface   = "hybrid",
-                endianness  = self.cpu.endianness
+                ethernet    = with_ethernet,
             )
-
-            # Software Interface.
-            self.ethmac = ethmac = self.get_module("ethcore_etherbone").mac
-            ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
-            ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
-            self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
-
-            # Add IRQs (if enabled).
-            if self.irq.enabled:
-                self.irq.add("ethmac", use_loc_if_exists=True)
-
-        # Ethernet ---------------------------------------------------------------------------------
+        # Ethernet only ----------------------------------------------------------------------------
         elif with_ethernet:
             # Ethernet MAC
             self.ethmac = ethmac = LiteEthMAC(
@@ -272,14 +259,6 @@ class SimSoC(SoCCore):
             if self.irq.enabled:
                 self.irq.add("ethmac", use_loc_if_exists=True)
 
-        # Etherbone --------------------------------------------------------------------------------
-        elif with_etherbone:
-            self.add_etherbone(
-                phy         = self.ethphy,
-                ip_address  = etherbone_ip_address,
-                mac_address = etherbone_mac_address
-            )
-
         # I2C --------------------------------------------------------------------------------------
         if with_i2c:
             pads = platform.request("i2c", 0)