From 8a0d50b03e2cd3316d4217ba3553df33fbf75620 Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Fri, 17 May 2024 09:46:23 +1000
Subject: [PATCH] tools/litex_json2dts_linux: add all soc sys_clk

Adds clocks for a downstream iclink soc, for example
when builder.add_json() has imported soc clocks.

Node names are as per devicetree fixed-clock.yaml bindings.
---
 litex/tools/litex_json2dts_linux.py | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py
index 94c7986cb..140ea9575 100755
--- a/litex/tools/litex_json2dts_linux.py
+++ b/litex/tools/litex_json2dts_linux.py
@@ -118,13 +118,18 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
 
     # Clocks ------------------------------------------------------------------------------------------
 
-    dts += """
-        sys_clk: pll {{
+    for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]:
+        name = c.removesuffix("config_clock_frequency") + "sys_clk"
+        dts += """
+        {name}: clock-{freq} {{
             compatible = "fixed-clock";
             #clock-cells = <0>;
-            clock-frequency  = <{sys_clk_freq}>;
+            clock-frequency  = <{freq}>;
         }};
-""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
+""".format(
+            name=name,
+            freq=d["constants"][c],
+        )
 
     # CPU ------------------------------------------------------------------------------------------