From 8a2646a54950248cfe28376ae06cb47f9053e77a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 27 Jan 2012 22:21:08 +0100 Subject: [PATCH] Remove explicit bus names --- milkymist/lm32/__init__.py | 4 ++-- milkymist/norflash/__init__.py | 2 +- milkymist/sram/__init__.py | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py index 324595419..29be0f65e 100644 --- a/milkymist/lm32/__init__.py +++ b/milkymist/lm32/__init__.py @@ -3,8 +3,8 @@ from migen.bus import wishbone class LM32: def __init__(self): - self.ibus = i = wishbone.Master("lm32i") - self.dbus = d = wishbone.Master("lm32d") + self.ibus = i = wishbone.Master() + self.dbus = d = wishbone.Master() self.interrupt = Signal(BV(32)) self.ext_break = Signal() self._inst = Instance("lm32_top", diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py index 0ee19ec27..5b3ad788a 100644 --- a/milkymist/norflash/__init__.py +++ b/milkymist/norflash/__init__.py @@ -4,7 +4,7 @@ from migen.corelogic import timeline class NorFlash: def __init__(self, adr_width, rd_timing): - self.bus = wishbone.Slave("norflash") + self.bus = wishbone.Slave() self.adr = Signal(BV(adr_width-1)) self.d = Signal(BV(16)) self.oe_n = Signal() diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py index 5071c4236..756b2c516 100644 --- a/milkymist/sram/__init__.py +++ b/milkymist/sram/__init__.py @@ -3,7 +3,7 @@ from migen.bus import wishbone class SRAM: def __init__(self, depth): - self.bus = wishbone.Slave("sram") + self.bus = wishbone.Slave() self.depth = depth def get_fragment(self):