From 8b86b16077c546aa6ac313cbca66927866f2ae73 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 20 Aug 2024 15:26:26 +0200
Subject: [PATCH] soc/cores/hyperbus: Make Rst synchronous to allow IO Reg
 (even if low speed).

---
 litex/soc/cores/hyperbus.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py
index 1895186c1..313030105 100644
--- a/litex/soc/cores/hyperbus.py
+++ b/litex/soc/cores/hyperbus.py
@@ -107,7 +107,7 @@ class HyperRAM(LiteXModule):
 
         # Rst.
         if hasattr(pads, "rst_n"):
-            self.comb += pads.rst_n.eq(1 & ~self.conf_rst)
+            self.sync += pads.rst_n.eq(1 & ~self.conf_rst)
 
         # CSn.
         self.comb += [