diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index 712cd9aba..1f8101d47 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -259,7 +259,7 @@ class Platform(XilinxPlatform):
 
     def create_programmer(self):
         bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
-        return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi)
+        return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 7e5ebc43c..7da31c872 100644
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -117,7 +117,7 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py
index 394e58675..dcb0001e1 100644
--- a/litex/boards/platforms/kc705.py
+++ b/litex/boards/platforms/kc705.py
@@ -549,7 +549,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
         self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py
index e112ca621..060caeb03 100644
--- a/litex/boards/platforms/nexys4ddr.py
+++ b/litex/boards/platforms/nexys4ddr.py
@@ -132,7 +132,7 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py
index c8604e9f4..6dbb9456f 100644
--- a/litex/boards/platforms/nexys_video.py
+++ b/litex/boards/platforms/nexys_video.py
@@ -232,7 +232,7 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)