From 8b9f03efba5210780f1458a88bdc725624159139 Mon Sep 17 00:00:00 2001 From: George Hilliard Date: Tue, 6 Jul 2021 08:39:57 -0500 Subject: [PATCH] clock/lattice_ecp5/ECP5PLL: Expose standby signal --- litex/soc/cores/clock/lattice_ecp5.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/clock/lattice_ecp5.py b/litex/soc/cores/clock/lattice_ecp5.py index ddf7d6591..d73f6536f 100644 --- a/litex/soc/cores/clock/lattice_ecp5.py +++ b/litex/soc/cores/clock/lattice_ecp5.py @@ -25,6 +25,7 @@ class ECP5PLL(Module): self.logger.info("Creating ECP5PLL.") self.reset = Signal() self.locked = Signal() + self.stdby = Signal() self.clkin_freq = None self.vcxo_freq = None self.nclkouts = 0 @@ -117,6 +118,7 @@ class ECP5PLL(Module): ("MFG_GMCREF_SEL", "2")], i_RST = self.reset, i_CLKI = self.clkin, + i_STDBY = self.stdby, o_LOCK = locked, p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1. p_CLKOS3_ENABLE = "ENABLED",