From 8c572d2b3e3ccd2c98fd45fd69d425e7b3fa3191 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 25 Jun 2020 11:13:24 +0200 Subject: [PATCH] targets: add fixed sdcard clock on boards with SDCard support. --- litex/boards/targets/nexys4ddr.py | 2 ++ litex/boards/targets/nexys_video.py | 2 ++ litex/boards/targets/ulx3s.py | 8 ++++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 303055d24..fb0224fb7 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -30,6 +30,7 @@ class _CRG(Module): self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_eth = ClockDomain() + self.clock_domains.cd_sdcard = ClockDomain() # # # @@ -41,6 +42,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_eth, 50e6) + pll.create_clkout(self.cd_sdcard, 10e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 22dd0366d..7312ba23e 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -30,6 +30,7 @@ class _CRG(Module): self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() + self.clock_domains.cd_sdcard = ClockDomain() # # # @@ -41,6 +42,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk100, 100e6) + pll.create_clkout(self.cd_sdcard, 10e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index da05ce2cf..ac4904506 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -32,7 +32,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq, with_usb_pll=False): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) - self.clock_domains.cd_clk10 = ClockDomain() # FIXME: for initial LiteSDCard tests. + self.clock_domains.cd_sdcard = ClockDomain() # # # @@ -46,9 +46,9 @@ class _CRG(Module): pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk10, 10e6) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) - self.specials += AsyncResetSynchronizer(self.cd_clk10, ~pll.locked | rst) + pll.create_clkout(self.cd_sdcard, 10e6) + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) + self.specials += AsyncResetSynchronizer(self.cd_sdcard, ~pll.locked | rst) # USB PLL if with_usb_pll: