From 8d6120c47683107e751ff7845f3d1f44b26efeb1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 8 Dec 2023 12:11:37 +0100 Subject: [PATCH] CHANGES: Update. --- CHANGES.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGES.md b/CHANGES.md index 8562ae949..7ce0bbe08 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -5,6 +5,7 @@ - liteeth/arp : Fixed response on table update. - litesata/us(p)sataphy : Fixed data_width=32 case. - clock/lattice_ecp5 : Fixed phase calculation. + - interconnect/axi : Fixed AXILite2CSR read access (1 CSR cycle instead of 2). [> Added -------- @@ -32,6 +33,7 @@ - soc/cores/clock : Added proper clock feedback support on Efinix TRIONPLL. - liteiclink/phy : Added Efinix support/examples on Trion/Titanium. - liteiclink/serwb : Reused Etherbone from LiteEth to avoid code duplication. + - interconnect : Added 64-bit support to Wishbone/AXI-Lite/AXI. [> Changed ----------