From 8d7196d567a1e8ba5f69a9e09d57d38f2b69c983 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 14 Nov 2021 09:18:53 +0100 Subject: [PATCH] cpu/eos_s3: Cleanup clocking. --- litex/soc/cores/cpu/eos_s3/core.py | 43 ++++++++++++++++-------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py index 29da9c543..69c54d256 100644 --- a/litex/soc/cores/cpu/eos_s3/core.py +++ b/litex/soc/cores/cpu/eos_s3/core.py @@ -13,6 +13,8 @@ from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU +class Open(Signal): pass + # EOS-S3 ------------------------------------------------------------------------------------------- class EOS_S3(CPU): @@ -43,22 +45,27 @@ class EOS_S3(CPU): # # # - # EOS-S3 Clocking. - self.clock_domains.cd_Sys_Clk0 = ClockDomain() - self.clock_domains.cd_Sys_Clk1 = ClockDomain() - - # EOS-S3 (Minimal) ------------------------------------------------------------------------- - Sys_Clk0_Rst = Signal() - Sys_Clk1_Rst = Signal() - WB_RST = Signal() - - class Open(Signal): pass + # EOS-S3 Clocking -------------------------------------------------------------------------- + pbus_rst = Signal() + eos_s3_0_rst = Signal() + eos_s3_1_rst = Signal() + self.clock_domains.cd_eos_s3_0 = ClockDomain() + self.clock_domains.cd_eos_s3_1 = ClockDomain() + self.specials += Instance("gclkbuff", + i_A = eos_s3_0_rst | pbus_rst, + o_Z = ResetSignal("eos_s3_0") + ) + self.specials += Instance("gclkbuff", + i_A = eos_s3_1_rst | pbus_rst, + o_Z = ResetSignal("eos_s3_1") + ) + # EOS-S3 Instance -------------------------------------------------------------------------- self.cpu_params = dict( # Wishbone Master. # ----------- - i_WB_CLK = ClockSignal("Sys_Clk0"), - o_WB_RST = WB_RST, + i_WB_CLK = ClockSignal("eos_s3_0"), + o_WB_RST = pbus_rst, o_WBs_ADR = Cat(Signal(2), self.pbus.adr), o_WBs_CYC = self.pbus.cyc, o_WBs_BYTE_STB = self.pbus.sel, @@ -85,10 +92,10 @@ class EOS_S3(CPU): # Clocking. # --------- - o_Sys_Clk0 = ClockSignal("Sys_Clk0"), - o_Sys_Clk0_Rst = Sys_Clk0_Rst, - o_Sys_Clk1 = ClockSignal("Sys_Clk1"), - o_Sys_Clk1_Rst = Sys_Clk1_Rst, + o_Sys_Clk0 = ClockSignal("eos_s3_0"), + o_Sys_Clk0_Rst = eos_s3_0_rst, + o_Sys_Clk1 = ClockSignal("eos_s3_1"), + o_Sys_Clk1_Rst = eos_s3_1_rst, # Packet FIFO. # ------------ @@ -148,9 +155,5 @@ class EOS_S3(CPU): i_WB_CLKS = 0 ) - self.specials += Instance("gclkbuff", - i_A = Sys_Clk0_Rst | WB_RST, - o_Z = self.cd_Sys_Clk0.rst) - def do_finalize(self): self.specials += Instance("qlal4s3b_cell_macro", **self.cpu_params)