From 8e86be1a6af41beb0d6296c1d4f3fe5b0d367f81 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 13 Sep 2012 13:14:27 +0200
Subject: [PATCH] add address parameter to migIo

---
 examples/de0_nano/top.py | 21 +++++++++------------
 examples/de1/top.py      |  4 ++--
 migScope/migIo.py        | 13 +++++++------
 migScope/trigger.py      |  2 +-
 4 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py
index c37e451d6..1b347ac63 100644
--- a/examples/de0_nano/top.py
+++ b/examples/de0_nano/top.py
@@ -42,7 +42,7 @@ from migen.bank.description import *
 import sys
 sys.path.append("../../")
 
-from migScope import trigger, recorder
+from migScope import trigger, recorder, migIo
 import spi2Csr
 
 from timings import *
@@ -65,7 +65,7 @@ dat_width = 16
 record_size = 1024
 
 # Csr Addr
-CONTROL_ADDR  = 0x0000
+MIGIO_ADDR  = 0x0000
 TRIGGER_ADDR  = 0x0200
 RECORDER_ADDR = 0x0400
 
@@ -74,11 +74,9 @@ RECORDER_ADDR = 0x0400
 #==============================================================================
 def get():
 
-	# Control Reg
-	control_reg0 = RegisterField("control_reg0", 32, reset=0, access_dev=READ_ONLY)
-	regs = [control_reg0]
-	bank0 = csrgen.Bank(regs,address=CONTROL_ADDR)
-
+	# migIo
+	migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
+	
 	# Trigger
 	term0 = trigger.Term(trig_width)
 	trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
@@ -88,11 +86,11 @@ def get():
 	
 	# Spi2Csr
 	spi2csr0 = spi2Csr.Spi2Csr(16,8)
-
+	
 	# Csr Interconnect
 	csrcon0 = csr.Interconnect(spi2csr0.csr, 
 			[
-				bank0.interface,
+				migIo0.bank.interface,
 				trigger0.bank.interface,
 				recorder0.bank.interface
 			])
@@ -107,9 +105,8 @@ def get():
 	
 	# Led
 	led0 = Signal(BV(8))
-	comb += [
-		led0.eq(control_reg0.field.r[:8])
-	]
+	comb += [led0.eq(migIo0.o)]
+
 	
 	
 	# Dat / Trig Bus
diff --git a/examples/de1/top.py b/examples/de1/top.py
index b1ba04f77..fd0b456f6 100644
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -65,7 +65,7 @@ dat_width = 16
 record_size = 1024
 
 # Csr Addr
-CONTROL_ADDR  = 0x0000
+MIGIO_ADDR  = 0x0000
 TRIGGER_ADDR  = 0x0200
 RECORDER_ADDR = 0x0400
 
@@ -75,7 +75,7 @@ RECORDER_ADDR = 0x0400
 def get():
 
 	# migIo
-	migIo0 = migIo.MigIo(8,"IO")
+	migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
 	
 	# Trigger
 	term0 = trigger.Term(trig_width)
diff --git a/migScope/migIo.py b/migScope/migIo.py
index 0a37869ff..0a6540b4d 100644
--- a/migScope/migIo.py
+++ b/migScope/migIo.py
@@ -5,11 +5,10 @@ from migen.bank.description import *
 
 
 class MigIo:
-	def __init__(self, width, mode = "IO"):
+	def __init__(self,address, width, mode = "IO"):
+		self.address = address
 		self.width = width
 		self.mode = mode
-		self.ireg = description.RegisterField("i", 0, READ_ONLY, WRITE_ONLY)
-		self.oreg = description.RegisterField("o", 0)
 		if "I" in self.mode:
 			self.i = Signal(BV(self.width))
 			self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
@@ -18,10 +17,12 @@ class MigIo:
 			self.o = Signal(BV(self.width))
 			self.oreg = description.RegisterField("o", self.width)
 			self.oreg.field.r.name_override = "ouptuts"
-		self.bank = csrgen.Bank([self.oreg, self.ireg])
+		self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
 
 	def get_fragment(self):
 		comb = []
-		comb += [self.ireg.field.w.eq(self.i)]
-		comb += [self.o.eq(self.oreg.field.r)]		
+		if "I" in self.mode:
+			comb += [self.ireg.field.w.eq(self.i)]
+		if "O" in self.mode:
+			comb += [self.o.eq(self.oreg.field.r)]
 		return Fragment(comb=comb) + self.bank.get_fragment()
diff --git a/migScope/trigger.py b/migScope/trigger.py
index 2e9d1da96..c67b973c7 100644
--- a/migScope/trigger.py
+++ b/migScope/trigger.py
@@ -249,7 +249,7 @@ class Trigger:
 		for object in sorted(objects):
 			if "_reg" in object:
 				regs.append(objects[object])
-		self.bank = csrgen.Bank(regs,address=address)
+		self.bank = csrgen.Bank(regs,address=self.address)
 		
 		# Update base addr
 		for port in self.ports: