From 8eb5e7b6c14d030c04cc6cfef31182fb49adbd03 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Wed, 28 Feb 2024 16:11:27 +0100 Subject: [PATCH] soc/cores/clock/colognechip: REF_CLK/OUT_CLK: int -> str --- litex/soc/cores/clock/colognechip.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/clock/colognechip.py b/litex/soc/cores/clock/colognechip.py index e4112aa8d..33e589df6 100644 --- a/litex/soc/cores/clock/colognechip.py +++ b/litex/soc/cores/clock/colognechip.py @@ -131,8 +131,8 @@ class GateMatePLL(LiteXModule): freqOutMHz = clkout_freq/1e6 self.specials += Instance("CC_PLL", - p_REF_CLK = freqInMHz, # reference input in MHz - p_OUT_CLK = freqOutMHz, # pll output frequency in MHz + p_REF_CLK = str(freqInMHz), # reference input in MHz + p_OUT_CLK = str(freqOutMHz), # pll output frequency in MHz p_LOW_JITTER = self._low_jitter, # 0: disable, 1: enable low jitter mode p_PERF_MD = self._perf_mode, # FPGA operation mode for VDD_PLL p_LOCK_REQ = self._lock_req, # Lock status required before PLL output enable