From 8f5c2dfbca17604984f7ff0a8f0bc94f3d841d6f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 20 Aug 2024 12:03:40 +0200 Subject: [PATCH] soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it). --- litex/soc/cores/hyperbus.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 80cffd058..3381aacd3 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -89,8 +89,8 @@ class HyperRAM(LiteXModule): # Tristates. # ---------- - dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq - rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds + dq = self.add_tristate(pads.dq, register=False) if not hasattr(pads.dq, "oe") else pads.dq + rwds = self.add_tristate(pads.rwds, register=False) if not hasattr(pads.rwds, "oe") else pads.rwds self.comb += [ # DQ. dq.o.eq( dq_o), @@ -357,10 +357,11 @@ class HyperRAM(LiteXModule): t = TristatePads(len(pad)) if register: for n in range(len(pad)): - self.specials += SDRTristate(pad, - o = t.o[n], - oe = t.oe, - i = t.i[n], + self.specials += SDRTristate(pad[n], + o = t.o[n], + oe = t.oe, + i = t.i[n], + clk = ClockSignal("sys"), ) else: self.specials += Tristate(pad,