From 8f5d2ba27f0e992d99b6016fd6faeab4ecff540e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 25 Feb 2021 09:06:26 +0100 Subject: [PATCH] tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided. This avoid corrupting pre-initialized contents or disabling memtest manually. --- litex/tools/litex_sim.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 319bed306..cbb503d91 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -216,9 +216,13 @@ class SimSoC(SoCCore): l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = False ) - # Reduce memtest size for simulation speedup - self.add_constant("MEMTEST_DATA_SIZE", 8*1024) - self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) + if sdram_init != []: + # Skip SDRAM test to avoid corrupting pre-initialized contents. + self.add_constant("SDRAM_TEST_DISABLE") + else: + # Reduce memtest size for simulation speedup + self.add_constant("MEMTEST_DATA_SIZE", 8*1024) + self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) #assert not (with_ethernet and with_etherbone)