diff --git a/lib/sata/link/test/Makefile b/lib/sata/link/test/Makefile
index d21efd7b3..bd6ef493f 100644
--- a/lib/sata/link/test/Makefile
+++ b/lib/sata/link/test/Makefile
@@ -8,13 +8,13 @@ CFLAGS =-Wall -O0
 
 crc_tb:
 	$(CC) $(CFLAGS) $(INC) -o crc crc.c
-	./crc /> crc_ref
 	$(CMD) crc_tb.py
 
 scrambler_tb:
 	$(CC) $(CFLAGS) $(INC) -o scrambler scrambler.c
-	./scrambler /> scrambler_ref
 	$(CMD) scrambler_tb.py
 
+all: crc_tb scrambler_tb
+
 clean:
-	rm crc crc_ref scrambler scrambler_ref
+	rm crc scrambler
diff --git a/lib/sata/link/test/common.py b/lib/sata/link/test/common.py
new file mode 100644
index 000000000..d95c8352a
--- /dev/null
+++ b/lib/sata/link/test/common.py
@@ -0,0 +1,11 @@
+def check(ref, res):
+	shift = 0
+	while((ref[0] != res[0]) and (len(res)>1)):
+		res.pop(0)
+		shift += 1
+	length = min(len(ref), len(res))
+	errors = 0
+	for i in range(length):
+		if ref.pop(0) != res.pop(0):
+			errors += 1
+	return shift, length, errors
diff --git a/lib/sata/link/test/crc.c b/lib/sata/link/test/crc.c
index 421cc00a0..f4f15954d 100644
--- a/lib/sata/link/test/crc.c
+++ b/lib/sata/link/test/crc.c
@@ -14,7 +14,7 @@ int main(int argc, char *argv[])
    crc = 0x52325032;
    data_count = 0;
 
-   while (data_count < 256)  {
+   while (data_count < 65536)  {
       data_count++;
 
       crc ^= data_in;
diff --git a/lib/sata/link/test/crc_tb.py b/lib/sata/link/test/crc_tb.py
index 459e4e173..6639a1939 100644
--- a/lib/sata/link/test/crc_tb.py
+++ b/lib/sata/link/test/crc_tb.py
@@ -1,28 +1,17 @@
-from subprocess import check_output
+import subprocess
 
 from migen.fhdl.std import *
 
 from lib.sata.std import *
 from lib.sata.link.crc import *
-
-def check(ref, res):
-	shift = 0
-	while((ref[0] != res[0]) and (len(res)>1)):
-		res.pop(0)
-		shift += 1
-	length = min(len(ref), len(res))
-	errors = 0
-	for i in range(length):
-		if ref.pop(0) != res.pop(0):
-			errors += 1
-	return shift, length, errors
+from lib.sata.link.test.common import check
 
 class TB(Module):
-	def __init__(self):
+	def __init__(self, length):
 		self.submodules.crc = SATACRC()
+		self.length = length
 
 	def gen_simulation(self, selfp):
-		
 	# init CRC
 		selfp.crc.d = 0x12345678
 		selfp.crc.ce = 1
@@ -31,15 +20,14 @@ class TB(Module):
 		selfp.crc.reset = 0
 
 	# get C code results
-		ref = []
-		f = open("crc_ref", "r")
-		for l in f:
-			ref.append(int(l, 16))
-		f.close()
+		p = subprocess.Popen(["./crc"], stdout=subprocess.PIPE)
+		out, err = p.communicate()
+		ref = [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]]
+
 
 	# log results
 		res = []
-		for i in range(256):
+		for i in range(self.length):
 			res.append(selfp.crc.value)
 			yield
 
@@ -49,4 +37,5 @@ class TB(Module):
 
 if __name__ == "__main__":
 	from migen.sim.generic import run_simulation
-	run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
+	length = 8192
+	run_simulation(TB(length), ncycles=length+100, vcd_name="my.vcd", keep_files=True)
diff --git a/lib/sata/link/test/scrambler.c b/lib/sata/link/test/scrambler.c
index cc96459b4..d8b0d8303 100644
--- a/lib/sata/link/test/scrambler.c
+++ b/lib/sata/link/test/scrambler.c
@@ -56,7 +56,7 @@ int main(int argc, char *argv[])
    unsigned char     next[32];
    context = 0xF0F6;
 
-   for (i = 0; i < 256; ++i)  {
+   for (i = 0; i < 65536; ++i)  {
       for (j = 0; j < 16; ++j)  {
          now[j] = (context >> j) & 0x01;
       }
diff --git a/lib/sata/link/test/scrambler_tb.py b/lib/sata/link/test/scrambler_tb.py
index 301b12516..6c9521f4a 100644
--- a/lib/sata/link/test/scrambler_tb.py
+++ b/lib/sata/link/test/scrambler_tb.py
@@ -1,28 +1,17 @@
-from subprocess import check_output
+import subprocess
 
 from migen.fhdl.std import *
 
 from lib.sata.std import *
 from lib.sata.link.scrambler import *
-
-def check(ref, res):
-	shift = 0
-	while((ref[0] != res[0]) and (len(res)>1)):
-		res.pop(0)
-		shift += 1
-	length = min(len(ref), len(res))
-	errors = 0
-	for i in range(length):
-		if ref.pop(0) != res.pop(0):
-			errors += 1
-	return shift, length, errors
+from lib.sata.link.test.common import check
 
 class TB(Module):
-	def __init__(self):
+	def __init__(self, length):
 		self.submodules.scrambler = SATAScrambler()
+		self.length = length
 
 	def gen_simulation(self, selfp):
-		
 	# init CRC
 		selfp.scrambler.ce = 1
 		selfp.scrambler.reset = 1
@@ -30,20 +19,16 @@ class TB(Module):
 		selfp.scrambler.reset = 0
 
 	# get C code results
-		ref = []
-		f = open("scrambler_ref", "r")
-		for l in f:
-			ref.append(int(l, 16))
-		f.close()
+		p = subprocess.Popen(["./scrambler"], stdout=subprocess.PIPE)
+		out, err = p.communicate()
+		ref = [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]]
 
 	# log results
 		yield
 		res = []
-		for i in range(256):
+		for i in range(self.length):
 			res.append(selfp.scrambler.value)
 			yield
-		for e in res:
-			print("%08x" %e)
 
 	# check results
 		s, l, e = check(ref, res)
@@ -51,4 +36,5 @@ class TB(Module):
 
 if __name__ == "__main__":
 	from migen.sim.generic import run_simulation
-	run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
+	length = 8192
+	run_simulation(TB(length), ncycles=length+100, vcd_name="my.vcd", keep_files=True)