diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py index 6eea41f19..e503fb564 100644 --- a/lib/sata/command/__init__.py +++ b/lib/sata/command/__init__.py @@ -1,14 +1,7 @@ from migen.fhdl.std import * from migen.genlib.fsm import FSM, NextState -from lib.sata.std import * -from lib.sata.transport.std import * - -regs = { - "WRITE_DMA_EXT" : 0x35, - "READ_DMA_EXT" : 0x25, - "IDENTIFY_DEVICE_DMA" : 0xEE -} +from lib.sata.common import * from_rx = [ ("dma_activate", 1), diff --git a/lib/sata/std.py b/lib/sata/common.py similarity index 55% rename from lib/sata/std.py rename to lib/sata/common.py index 6bfbeccb3..0c839f18e 100644 --- a/lib/sata/std.py +++ b/lib/sata/common.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.flow.actor import * +# PHY / Link Layers primitives = { "ALIGN" : 0x7B4A4ABC, "CONT" : 0X9999AA7C, @@ -31,9 +32,6 @@ def decode_primitive(dword): return k return "" -def ones(width): - return 2**width-1 - def phy_layout(dw): layout = [ ("data", dw), @@ -48,6 +46,66 @@ def link_layout(dw): ] return EndpointDescription(layout, packetized=True) +# Transport Layer +fis_types = { + "REG_H2D": 0x27, + "REG_D2H": 0x34, + "DMA_ACTIVATE_D2H": 0x39, + "DATA": 0x46 +} + +class FISField(): + def __init__(self, dword, offset, width): + self.dword = dword + self.offset = offset + self.width = width + +fis_reg_h2d_cmd_len = 5 +fis_reg_h2d_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4), + "c": FISField(0, 15, 1), + "command": FISField(0, 16, 8), + "features_lsb": FISField(0, 24, 8), + + "lba_lsb": FISField(1, 0, 24), + "device": FISField(1, 24, 8), + + "lba_msb": FISField(2, 0, 24), + "features_msb": FISField(2, 24, 8), + + "count": FISField(3, 0, 16), + "icc": FISField(3, 16, 8), + "control": FISField(3, 24, 8) +} + +fis_reg_d2h_cmd_len = 5 +fis_reg_d2h_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4), + "i": FISField(0, 14, 1), + "status": FISField(0, 16, 8), + "error": FISField(0, 24, 8), + + "lba_lsb": FISField(1, 0, 24), + "device": FISField(1, 24, 8), + + "lba_msb": FISField(2, 0, 24), + + "count": FISField(3, 0, 16) +} + +fis_dma_activate_d2h_cmd_len = 1 +fis_dma_activate_d2h_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4) +} + +fis_data_cmd_len = 1 +fis_data_layout = { + "type": FISField(0, 0, 8) +} + def transport_tx_layout(dw): layout = [ ("type", 8), @@ -78,6 +136,13 @@ def transport_rx_layout(dw): ] return EndpointDescription(layout, packetized=True) +# Command Layer constants / functions +regs = { + "WRITE_DMA_EXT" : 0x35, + "READ_DMA_EXT" : 0x25, + "IDENTIFY_DEVICE_DMA" : 0xEE +} + def command_tx_layout(dw): layout = [ ("write", 1), diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py index 47a8f29c4..4a429ee00 100644 --- a/lib/sata/link/__init__.py +++ b/lib/sata/link/__init__.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.genlib.fsm import FSM, NextState from migen.actorlib.fifo import SyncFIFO -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link.crc import SATACRCInserter, SATACRCChecker from lib.sata.link.scrambler import SATAScrambler from lib.sata.link.cont import SATACONTInserter, SATACONTRemover diff --git a/lib/sata/link/cont.py b/lib/sata/link/cont.py index ae6bb5719..95e7c679a 100644 --- a/lib/sata/link/cont.py +++ b/lib/sata/link/cont.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.genlib.misc import optree -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link.scrambler import Scrambler class SATACONTInserter(Module): diff --git a/lib/sata/link/crc.py b/lib/sata/link/crc.py index f948fdfb0..9768dcee1 100644 --- a/lib/sata/link/crc.py +++ b/lib/sata/link/crc.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.genlib.misc import optree from migen.actorlib.crc import CRCInserter, CRCChecker -from lib.sata.std import * +from lib.sata.common import * class CRCEngine(Module): """Cyclic Redundancy Check Engine diff --git a/lib/sata/link/scrambler.py b/lib/sata/link/scrambler.py index 9d8783db6..127e5a0a8 100644 --- a/lib/sata/link/scrambler.py +++ b/lib/sata/link/scrambler.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.genlib.misc import optree -from lib.sata.std import * +from lib.sata.common import * @DecorateModule(InsertCE) class Scrambler(Module): diff --git a/lib/sata/phy/k7sataphy/__init__.py b/lib/sata/phy/k7sataphy/__init__.py index d1c8c8ffc..0759ccb7e 100644 --- a/lib/sata/phy/k7sataphy/__init__.py +++ b/lib/sata/phy/k7sataphy/__init__.py @@ -1,6 +1,6 @@ from migen.fhdl.std import * -from lib.sata.std import * +from lib.sata.common import * from lib.sata.phy.k7sataphy.gtx import K7SATAPHYGTX from lib.sata.phy.k7sataphy.crg import K7SATAPHYCRG from lib.sata.phy.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl diff --git a/lib/sata/phy/k7sataphy/crg.py b/lib/sata/phy/k7sataphy/crg.py index 25a2f7845..2166fa774 100644 --- a/lib/sata/phy/k7sataphy/crg.py +++ b/lib/sata/phy/k7sataphy/crg.py @@ -4,7 +4,7 @@ from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.fsm import FSM, NextState -from lib.sata.std import * +from lib.sata.common import * from lib.sata.phy.k7sataphy.gtx import GTXE2_COMMON class K7SATAPHYCRG(Module): diff --git a/lib/sata/phy/k7sataphy/ctrl.py b/lib/sata/phy/k7sataphy/ctrl.py index 3179416d9..a3658c6e0 100644 --- a/lib/sata/phy/k7sataphy/ctrl.py +++ b/lib/sata/phy/k7sataphy/ctrl.py @@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.fsm import FSM, NextState from migen.flow.actor import Sink, Source -from lib.sata.std import * +from lib.sata.common import * def us(t, clk_freq): clk_period_us = 1000000/clk_freq diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py index 3a3683c70..8facc6e02 100644 --- a/lib/sata/phy/k7sataphy/datapath.py +++ b/lib/sata/phy/k7sataphy/datapath.py @@ -3,7 +3,7 @@ from migen.genlib.misc import chooser from migen.actorlib.fifo import AsyncFIFO from migen.flow.actor import Sink, Source -from lib.sata.std import * +from lib.sata.common import * class K7SATAPHYDatapathRX(Module): def __init__(self): diff --git a/lib/sata/phy/k7sataphy/gtx.py b/lib/sata/phy/k7sataphy/gtx.py index 101303130..1d1077398 100644 --- a/lib/sata/phy/k7sataphy/gtx.py +++ b/lib/sata/phy/k7sataphy/gtx.py @@ -1,7 +1,10 @@ from migen.fhdl.std import * from migen.genlib.cdc import * -from lib.sata.std import * +from lib.sata.common import * + +def ones(width): + return 2**width-1 class _PulseSynchronizer(PulseSynchronizer): def __init__(self, i, idomain, o, odomain): diff --git a/lib/sata/test/bfm.py b/lib/sata/test/bfm.py index 435ac2b4c..3a18633a6 100644 --- a/lib/sata/test/bfm.py +++ b/lib/sata/test/bfm.py @@ -2,9 +2,7 @@ import subprocess from migen.fhdl.std import * -from lib.sata.std import * -from lib.sata.transport.std import * - +from lib.sata.common import * from lib.sata.test.common import * class PHYDword: @@ -373,12 +371,6 @@ class TransportLayer(Module): else: self.command_callback(fis) -regs = { - "WRITE_DMA_EXT" : 0x35, - "READ_DMA_EXT" : 0x25, - "IDENTIFY_DEVICE_DMA" : 0xEE -} - class CommandLayer(Module): def __init__(self, transport, debug=False): self.transport = transport diff --git a/lib/sata/test/command_tb.py b/lib/sata/test/command_tb.py index 4849d961a..302ab0d63 100644 --- a/lib/sata/test/command_tb.py +++ b/lib/sata/test/command_tb.py @@ -4,7 +4,7 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.sim.generic import run_simulation -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link import SATALink from lib.sata.transport import SATATransport from lib.sata.command import SATACommand diff --git a/lib/sata/test/common.py b/lib/sata/test/common.py index 80986b44f..69d0211bc 100644 --- a/lib/sata/test/common.py +++ b/lib/sata/test/common.py @@ -1,6 +1,6 @@ import random -from lib.sata.std import * +from lib.sata.common import * def seed_to_data(seed, random=True): if random: diff --git a/lib/sata/test/crc_tb.py b/lib/sata/test/crc_tb.py index 0ce17dcac..995250ad4 100644 --- a/lib/sata/test/crc_tb.py +++ b/lib/sata/test/crc_tb.py @@ -2,7 +2,7 @@ import subprocess from migen.fhdl.std import * -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link.crc import * from lib.sata.test.common import * diff --git a/lib/sata/test/link_tb.py b/lib/sata/test/link_tb.py index d56358385..3696884be 100644 --- a/lib/sata/test/link_tb.py +++ b/lib/sata/test/link_tb.py @@ -4,7 +4,7 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.sim.generic import run_simulation -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link import SATALink from lib.sata.test.bfm import * diff --git a/lib/sata/test/scrambler_tb.py b/lib/sata/test/scrambler_tb.py index 78541ca88..68e4315e2 100644 --- a/lib/sata/test/scrambler_tb.py +++ b/lib/sata/test/scrambler_tb.py @@ -2,7 +2,7 @@ import subprocess from migen.fhdl.std import * -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link.scrambler import * from lib.sata.test.common import * diff --git a/lib/sata/test/transport_tb.py b/lib/sata/test/transport_tb.py index 392dbdbdc..b49d1ed5e 100644 --- a/lib/sata/test/transport_tb.py +++ b/lib/sata/test/transport_tb.py @@ -4,7 +4,7 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.sim.generic import run_simulation -from lib.sata.std import * +from lib.sata.common import * from lib.sata.link import SATALink from lib.sata.transport import SATATransport diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py index 26570f6e5..fe98479d2 100644 --- a/lib/sata/transport/__init__.py +++ b/lib/sata/transport/__init__.py @@ -1,8 +1,7 @@ from migen.fhdl.std import * from migen.genlib.fsm import FSM, NextState -from lib.sata.std import * -from lib.sata.transport.std import * +from lib.sata.common import * def _encode_cmd(obj, layout, signal): r = [] diff --git a/lib/sata/transport/std.py b/lib/sata/transport/std.py deleted file mode 100644 index b8f53f6e3..000000000 --- a/lib/sata/transport/std.py +++ /dev/null @@ -1,58 +0,0 @@ -fis_types = { - "REG_H2D": 0x27, - "REG_D2H": 0x34, - "DMA_ACTIVATE_D2H": 0x39, - "DATA": 0x46 -} - -class FISField(): - def __init__(self, dword, offset, width): - self.dword = dword - self.offset = offset - self.width = width - -fis_reg_h2d_cmd_len = 5 -fis_reg_h2d_layout = { - "type": FISField(0, 0, 8), - "pm_port": FISField(0, 8, 4), - "c": FISField(0, 15, 1), - "command": FISField(0, 16, 8), - "features_lsb": FISField(0, 24, 8), - - "lba_lsb": FISField(1, 0, 24), - "device": FISField(1, 24, 8), - - "lba_msb": FISField(2, 0, 24), - "features_msb": FISField(2, 24, 8), - - "count": FISField(3, 0, 16), - "icc": FISField(3, 16, 8), - "control": FISField(3, 24, 8) -} - -fis_reg_d2h_cmd_len = 5 -fis_reg_d2h_layout = { - "type": FISField(0, 0, 8), - "pm_port": FISField(0, 8, 4), - "i": FISField(0, 14, 1), - "status": FISField(0, 16, 8), - "error": FISField(0, 24, 8), - - "lba_lsb": FISField(1, 0, 24), - "device": FISField(1, 24, 8), - - "lba_msb": FISField(2, 0, 24), - - "count": FISField(3, 0, 16) -} - -fis_dma_activate_d2h_cmd_len = 1 -fis_dma_activate_d2h_layout = { - "type": FISField(0, 0, 8), - "pm_port": FISField(0, 8, 4) -} - -fis_data_cmd_len = 1 -fis_data_layout = { - "type": FISField(0, 0, 8) -} diff --git a/targets/test.py b/targets/test.py index 53a558226..e5e92e4cb 100644 --- a/targets/test.py +++ b/targets/test.py @@ -8,7 +8,7 @@ from migen.bank.description import * from miscope.uart2wishbone import UART2Wishbone from misoclib import identifier -from lib.sata.std import * +from lib.sata.common import * from lib.sata.phy.k7sataphy import K7SATAPHY from migen.genlib.cdc import *