diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 516ee4106..12027bfc8 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -54,8 +54,8 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs):
-        platform = arty.Platform(toolchain=toolchain)
+    def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs):
+        platform = arty.Platform(variant=variant, toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -107,6 +107,7 @@ def main():
     parser.add_argument("--toolchain",        default="vivado",     help="Toolchain use to build (default: vivado)")
     parser.add_argument("--build",            action="store_true",  help="Build bitstream")
     parser.add_argument("--load",             action="store_true",  help="Load bitstream")
+    parser.add_argument("--variant",          default="a7-35",      help="Board variant: a7-35 (default) or a7-100")
     parser.add_argument("--sys-clk-freq",     default=100e6,        help="System clock frequency (default: 100MHz)")
     parser.add_argument("--with-ethernet",    action="store_true",  help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",   action="store_true",  help="Enable Etherbone support")
@@ -120,6 +121,7 @@ def main():
 
     assert not (args.with_ethernet and args.with_etherbone)
     soc = BaseSoC(
+        variant        = args.variant,
         toolchain      = args.toolchain,
         sys_clk_freq   = int(float(args.sys_clk_freq)),
         with_ethernet  = args.with_ethernet,