From 901428f5a99c9a771dd84063e8d994415a46586a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 21 Mar 2022 18:03:40 +0100 Subject: [PATCH] soc/add_ethernet: Fix add_ethernet. --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 91915b8f3..d197c5d47 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1479,7 +1479,7 @@ class LiteXSoC(SoC): "eth_rx": phy_cd + "_rx"})(ethmac) setattr(self.submodules, name, ethmac) # Compute Regions size and add it to the SoC. - ethmac_region_size = (ethmac.rx_slots.read() + ethmac.tx_slots.read())*ethmac.slot_size.read() + ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False) self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) # Add IRQs (if enabled).