From 90184b22d2f7e88fd4e76ae142480756038ef2cc Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 6 Mar 2012 16:45:44 +0100 Subject: [PATCH] fhdl/verilog: fix signed constant conversion --- migen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index e68071aec..854da372d 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -21,7 +21,7 @@ def _printexpr(ns, node): if node.n >= 0: return str(node.bv) + str(node.n) else: - return "-" + str(node.bv) + str(-self.n) + return "-" + str(node.bv) + str(-node.n) elif isinstance(node, Signal): return ns.get_name(node) elif isinstance(node, _Operator):