diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index 4758cccbb..50ca77ed2 100644
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -23,7 +23,7 @@ def axi_fifo_ctrl_layout():
         ("wrissuecapen",    1, DIR_S_TO_M),
     ]
 
-# SoC Zync -----------------------------------------------------------------------------------------
+# SoC Zynq -----------------------------------------------------------------------------------------
 
 class SoCZynq(SoCCore):
     SoCCore.mem_map["csr"] = 0x00000000