diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 0dc8ff9b0..a8ac01edb 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -42,7 +42,7 @@ class SoCSDRAM(SoCCore):
             raise FinalizeError
         self._wb_sdram_ifs.append(interface)
 
-    def register_sdram(self, phy, geom_settings, timing_settings, use_full_memory_we=True, **kwargs):
+    def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
         assert not self._sdram_phy
         self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
 
@@ -99,7 +99,7 @@ class SoCSDRAM(SoCCore):
             # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
             # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
             from litex.build.xilinx.vivado import XilinxVivadoToolchain
-            if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we:
+            if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
                 from migen.fhdl.simplify import FullMemoryWE
                 self.submodules.l2_cache = FullMemoryWE()(l2_cache)
             else: