From 905be504514359ad4b354484982ee4a4a0e747e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 3 Mar 2015 09:49:57 +0100 Subject: [PATCH] sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy --- misoclib/mem/sdram/core/__init__.py | 4 ++-- misoclib/mem/sdram/{bus => core}/lasmibus.py | 0 misoclib/mem/sdram/core/lasmicon/__init__.py | 3 ++- .../mem/sdram/core/{lasmicon/crossbar.py => lasmixbar.py} | 4 ++-- misoclib/mem/sdram/core/minicon/__init__.py | 2 +- misoclib/mem/sdram/{bus => phy}/dfi.py | 0 misoclib/mem/sdram/phy/dfii.py | 2 +- misoclib/mem/sdram/phy/gensdrphy.py | 2 +- misoclib/mem/sdram/phy/k7ddrphy.py | 2 +- misoclib/mem/sdram/phy/s6ddrphy.py | 2 +- misoclib/mem/sdram/test/abstract_transactions_lasmi.py | 2 +- misoclib/mem/sdram/test/bankmachine_tb.py | 2 +- misoclib/mem/sdram/test/lasmicon_df_tb.py | 2 +- misoclib/mem/sdram/test/lasmicon_tb.py | 2 +- misoclib/mem/sdram/test/lasmicon_wb.py | 2 +- misoclib/soc/sdram.py | 1 - 16 files changed, 16 insertions(+), 16 deletions(-) rename misoclib/mem/sdram/{bus => core}/lasmibus.py (100%) rename misoclib/mem/sdram/core/{lasmicon/crossbar.py => lasmixbar.py} (98%) rename misoclib/mem/sdram/{bus => phy}/dfi.py (100%) diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py index a4b526c5e..f31277528 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoclib/mem/sdram/core/__init__.py @@ -4,7 +4,7 @@ from migen.bank.description import * from misoclib.mem.sdram.phy import dfii from misoclib.mem.sdram.core import minicon, lasmicon -from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar +from misoclib.mem.sdram.core import lasmixbar class SDRAMCore(Module, AutoCSR): def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs): @@ -18,7 +18,7 @@ class SDRAMCore(Module, AutoCSR): self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, sdram_geom, sdram_timing, **kwargs) self.comb += Record.connect(controller.dfi, self.dfii.slave) - self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits) + self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits) # MINICON elif ramcon_type == "minicon": diff --git a/misoclib/mem/sdram/bus/lasmibus.py b/misoclib/mem/sdram/core/lasmibus.py similarity index 100% rename from misoclib/mem/sdram/bus/lasmibus.py rename to misoclib/mem/sdram/core/lasmibus.py diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py index bfe3a1309..393e218b3 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoclib/mem/sdram/core/lasmicon/__init__.py @@ -1,6 +1,7 @@ from migen.fhdl.std import * -from misoclib.mem.sdram.bus import dfi, lasmibus +from misoclib.mem.sdram.phy import dfi +from misoclib.mem.sdram.core import lasmibus from misoclib.mem.sdram.core.lasmicon.refresher import * from misoclib.mem.sdram.core.lasmicon.bankmachine import * from misoclib.mem.sdram.core.lasmicon.multiplexer import * diff --git a/misoclib/mem/sdram/core/lasmicon/crossbar.py b/misoclib/mem/sdram/core/lasmixbar.py similarity index 98% rename from misoclib/mem/sdram/core/lasmicon/crossbar.py rename to misoclib/mem/sdram/core/lasmixbar.py index e4414900e..d4da80939 100644 --- a/misoclib/mem/sdram/core/lasmicon/crossbar.py +++ b/misoclib/mem/sdram/core/lasmixbar.py @@ -3,7 +3,7 @@ from migen.genlib import roundrobin from migen.genlib.record import * from migen.genlib.misc import optree -from misoclib.mem.sdram.bus.lasmibus import Interface +from misoclib.mem.sdram.core.lasmibus import Interface def _getattr_all(l, attr): it = iter(l) @@ -13,7 +13,7 @@ def _getattr_all(l, attr): raise ValueError return r -class Crossbar(Module): +class LASMIxbar(Module): def __init__(self, controllers, cba_shift): self._controllers = controllers self._cba_shift = cba_shift diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/core/minicon/__init__.py index 1f7660eeb..19a76373e 100644 --- a/misoclib/mem/sdram/core/minicon/__init__.py +++ b/misoclib/mem/sdram/core/minicon/__init__.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.fsm import FSM, NextState -from misoclib.mem.sdram.bus import dfi as dfibus +from misoclib.mem.sdram.phy import dfi as dfibus class _AddressSlicer: def __init__(self, col_a, bank_a, row_a, address_align): diff --git a/misoclib/mem/sdram/bus/dfi.py b/misoclib/mem/sdram/phy/dfi.py similarity index 100% rename from misoclib/mem/sdram/bus/dfi.py rename to misoclib/mem/sdram/phy/dfi.py diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoclib/mem/sdram/phy/dfii.py index c3fa216f9..abe4ce370 100644 --- a/misoclib/mem/sdram/phy/dfii.py +++ b/misoclib/mem/sdram/phy/dfii.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bank.description import * -from misoclib.mem.sdram.bus import dfi +from misoclib.mem.sdram.phy import dfi class PhaseInjector(Module, AutoCSR): def __init__(self, phase): diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py index f7af68d40..befd6509c 100644 --- a/misoclib/mem/sdram/phy/gensdrphy.py +++ b/misoclib/mem/sdram/phy/gensdrphy.py @@ -25,7 +25,7 @@ from migen.fhdl.std import * from migen.genlib.record import * from migen.fhdl.specials import * -from misoclib.mem.sdram.bus.dfi import * +from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram class GENSDRPHY(Module): diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py b/misoclib/mem/sdram/phy/k7ddrphy.py index 420219445..8d86931da 100644 --- a/misoclib/mem/sdram/phy/k7ddrphy.py +++ b/misoclib/mem/sdram/phy/k7ddrphy.py @@ -3,7 +3,7 @@ from migen.fhdl.std import * from migen.bank.description import * -from misoclib.mem.sdram.bus.dfi import * +from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram class K7DDRPHY(Module, AutoCSR): diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py index 1d5fe0f73..aacdf04cb 100644 --- a/misoclib/mem/sdram/phy/s6ddrphy.py +++ b/misoclib/mem/sdram/phy/s6ddrphy.py @@ -17,7 +17,7 @@ from migen.fhdl.std import * from migen.genlib.record import * -from misoclib.mem.sdram.bus.dfi import * +from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram class S6DDRPHY(Module): diff --git a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py b/misoclib/mem/sdram/test/abstract_transactions_lasmi.py index 6bfb1fdba..cdd78e707 100644 --- a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py +++ b/misoclib/mem/sdram/test/abstract_transactions_lasmi.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.bus import lasmibus +from misoclib.mem.sdram.core import lasmibus def my_generator(n): bank = n % 4 diff --git a/misoclib/mem/sdram/test/bankmachine_tb.py b/misoclib/mem/sdram/test/bankmachine_tb.py index 12ae5da0a..77841e433 100644 --- a/misoclib/mem/sdram/test/bankmachine_tb.py +++ b/misoclib/mem/sdram/test/bankmachine_tb.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.bus import lasmibus +from misoclib.mem.sdram.code import lasmibus from misoclib.mem.sdram.core.lasmicon.bankmachine import * from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger diff --git a/misoclib/mem/sdram/test/lasmicon_df_tb.py b/misoclib/mem/sdram/test/lasmicon_df_tb.py index e06722f0c..d239d49a0 100644 --- a/misoclib/mem/sdram/test/lasmicon_df_tb.py +++ b/misoclib/mem/sdram/test/lasmicon_df_tb.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.bus import lasmibus +from misoclib.mem.sdram.core import lasmibus from misoclib.mem.sdram.core.lasmicon import * from misoclib.mem.sdram.frontend import dma_lasmi diff --git a/misoclib/mem/sdram/test/lasmicon_tb.py b/misoclib/mem/sdram/test/lasmicon_tb.py index a102b07c5..0352c0609 100644 --- a/misoclib/mem/sdram/test/lasmicon_tb.py +++ b/misoclib/mem/sdram/test/lasmicon_tb.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.bus import lasmibus +from misoclib.mem.sdram.core import lasmibus from misoclib.mem.sdram.core.lasmicon import * from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/mem/sdram/test/lasmicon_wb.py b/misoclib/mem/sdram/test/lasmicon_wb.py index 978655dcb..dae6c6342 100644 --- a/misoclib/mem/sdram/test/lasmicon_wb.py +++ b/misoclib/mem/sdram/test/lasmicon_wb.py @@ -3,7 +3,7 @@ from migen.bus import wishbone from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.mem.sdram.bus import lasmibus +from misoclib.mem.sdram.core import lasmibus from misoclib.mem.sdram.core.lasmicon import * from misoclib.mem.sdram.frontend import wishbone2lasmi diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index ac4024c34..4acc42975 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -2,7 +2,6 @@ from migen.fhdl.std import * from migen.bus import wishbone, csr from migen.genlib.record import * -from misoclib.mem.sdram.bus import dfi, lasmibus from misoclib.mem.sdram.core import SDRAMCore from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi from misoclib.soc import SoC, mem_decoder