diff --git a/litex/boards/platforms/ulx3s.py b/litex/boards/platforms/ulx3s.py index faf26ca75..c5b5cdfe4 100644 --- a/litex/boards/platforms/ulx3s.py +++ b/litex/boards/platforms/ulx3s.py @@ -10,7 +10,7 @@ from litex.build.lattice.programmer import UJProg # IOs ---------------------------------------------------------------------------------------------- -_io = [ +_io_common = [ ("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")), ("rst", 0, Pins("R1"), IOStandard("LVCMOS33")), @@ -28,23 +28,6 @@ _io = [ Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33")) ), - ("spisdcard", 0, - Subsignal("clk", Pins("J1")), - Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), - Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), - Misc("SLEWRATE=FAST"), - IOStandard("LVCMOS33"), - ), - - ("sdcard", 0, - Subsignal("clk", Pins("J1")), - Subsignal("cmd", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), - Misc("SLEWRATE=FAST"), - IOStandard("LVCMOS33"), - ), - ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( @@ -109,14 +92,56 @@ _io = [ ), ] +_io_1_7 = [ + ("spisdcard", 0, + Subsignal("clk", Pins("J1")), + Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), + Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + + ("sdcard", 0, + Subsignal("clk", Pins("J1")), + Subsignal("cmd", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), +] + +_io_2_0 = [ + ("spisdcard", 0, + Subsignal("clk", Pins("H2")), + Subsignal("mosi", Pins("J1"), Misc("PULLMODE=UP")), + Subsignal("cs_n", Pins("K2"), Misc("PULLMODE=UP")), + Subsignal("miso", Pins("J3"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + + ("sdcard", 0, + Subsignal("clk", Pins("H2")), + Subsignal("cmd", Pins("J1"), Misc("PULLMODE=UP")), + Subsignal("data", Pins("J3 H1 K1 K2"), Misc("PULLMODE=UP")), + Subsignal("cd", Pins("N5")), + Subsignal("wp", Pins("P5")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), +] + # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): default_clk_name = "clk25" default_clk_period = 1e9/25e6 - def __init__(self, device="LFE5U-45F", **kwargs): + def __init__(self, device="LFE5U-45F", revision="2.0", **kwargs): assert device in ["LFE5U-25F", "LFE5U-45F", "LFE5U-85F"] + assert revision in ["1.7", "2.0"] + _io = _io_common + {"1.7": _io_1_7, "2.0": _io_2_0}[revision] LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs) def create_programmer(self): diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 69cfc2a41..c327b877e 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -30,7 +30,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -39,9 +39,9 @@ class _CRG(Module): pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py index 25598e833..6edf2120f 100755 --- a/litex/boards/targets/icebreaker.py +++ b/litex/boards/targets/icebreaker.py @@ -29,7 +29,9 @@ from litex.soc.cores.up5kspram import Up5kSPRAM from litex.soc.cores.spi_flash import SpiFlash from litex.soc.cores.clock import iCE40PLL from litex.soc.integration.soc_core import * +from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser kB = 1024 mB = 1024*kB @@ -39,41 +41,37 @@ mB = 1024*kB class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_por = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) # # # - # Clocking + # Clk/Rst clk12 = platform.request("clk12") rst_n = platform.request("user_btn_n") - if sys_clk_freq == 12e6: - self.comb += self.cd_sys.clk.eq(clk12) - else: - self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD") - pll.register_clkin(clk12, 12e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq) # Power On Reset - por_cycles = 4096 - por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1) - self.comb += self.cd_por.clk.eq(self.cd_sys.clk) - platform.add_period_constraint(self.cd_por.clk, 1e9/sys_clk_freq) - self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1)) - self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n) - self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0)) + por_count = Signal(16, reset=2**16-1) + por_done = Signal() + self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += por_done.eq(por_count == 0) + self.sync.por += If(~por_done, por_count.eq(por_count - 1)) + + # PLL + self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD") + self.comb += pll.reset.eq(~rst_n) + pll.register_clkin(clk12, 12e6) + pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False) + self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked) + platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - SoCCore.mem_map = { - "sram": 0x10000000, - "spiflash": 0x20000000, - "csr": 0xf0000000, - } + mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} def __init__(self, bios_flash_offset, **kwargs): sys_clk_freq = int(24e6) platform = icebreaker.Platform() + platform.add_extension(icebreaker.break_off_pmod) # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 @@ -92,30 +90,32 @@ class BaseSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq) # 128KB SPRAM (used as SRAM) --------------------------------------------------------------- - self.submodules.spram = Up5kSPRAM(size=64*kB) - self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB) + self.submodules.spram = Up5kSPRAM(size=128*kB) + self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB)) # SPI Flash -------------------------------------------------------------------------------- - self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little") - self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=16*mB) - self.add_csr("spiflash") + self.add_spi_flash(mode="1x", dummy_cycles=8) # Add ROM linker region -------------------------------------------------------------------- - self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker") + self.bus.add_region("rom", SoCRegion( + origin = self.mem_map["spiflash"] + bios_flash_offset, + size = 32*kB, + linker = True) + ) # Leds ------------------------------------------------------------------------------------- - counter = Signal(32) - self.sync += counter.eq(counter + 1) - self.comb += platform.request("user_ledr_n").eq(counter[26]) - self.comb += platform.request("user_ledg_n").eq(~counter[26]) + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") # Flash -------------------------------------------------------------------------------------------- def flash(bios_flash_offset): from litex.build.lattice.programmer import IceStormProgrammer prog = IceStormProgrammer() - prog.flash(bios_flash_offset, "soc_basesoc_icebreaker/software/bios/bios.bin") - prog.flash(0x00000000, "soc_basesoc_icebreaker/gateware/top.bin") + prog.flash(bios_flash_offset, "build/icebreaker/software/bios/bios.bin") + prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin") exit() # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 320d0ca78..5aa2189cb 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -32,7 +32,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() # # # @@ -41,9 +41,9 @@ class _CRG(Module): pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 83a4e684f..a13e85f6f 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # @@ -40,7 +40,7 @@ class _CRG(Module): self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 200e6, with_reset=False) pll.create_clkout(self.cd_eth, 200e6) self.specials += [ @@ -49,10 +49,10 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), + AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] - self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys) + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index d5e4d31a1..dfd2f39cf 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() self.clock_domains.cd_eth = ClockDomain() @@ -42,11 +42,11 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_clk100, 100e6) pll.create_clkout(self.cd_eth, 50e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 06f70139e..18e4d4db1 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # @@ -42,10 +42,10 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_eth, 50e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index a0fdc2e51..b77af2f4d 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_idelay = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() # # # @@ -42,10 +42,10 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_clk100, 100e6) - self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 6a5404021..31126c059 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -58,11 +58,11 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. else: pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # USB PLL if with_usb_pll: self.submodules.usb_pll = usb_pll = ECP5PLL() + self.comb += usb_pll.reset.eq(rst) usb_pll.register_clkin(clk25, 25e6) self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain() @@ -79,10 +79,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, device="LFE5U-45F", toolchain="trellis", + def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs): - platform = ulx3s.Platform(device=device, toolchain=toolchain) + platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -132,6 +132,7 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") + parser.add_argument("--revision", default="2.0", type=str, help="Board revision 2.0 (default), 1.7") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") @@ -143,7 +144,7 @@ def main(): trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(device=args.device, toolchain=args.toolchain, + soc = BaseSoC(device=args.device, revision=args.revision, toolchain=args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), sdram_module_cls = args.sdram_module, sdram_rate = args.sdram_rate, diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 5f6a083c4..fa751d256 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -56,6 +56,7 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() + self.comb += pll.reset.eq(~por_done | ~rst_n) pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 25e6) @@ -70,15 +71,14 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, toolchain="trellis", **kwargs): + def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, eth_phy=0, toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain, device=device) # FIXME: adapt integrated rom size for Microwatt @@ -112,13 +112,16 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) - # Ethernet --------------------------------------------------------------------------------- - if with_ethernet: + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) + clock_pads = self.platform.request("eth_clocks", eth_phy), + pads = self.platform.request("eth", eth_phy)) self.add_csr("ethphy") - self.add_ethernet(phy=self.ethphy) + if with_ethernet: + self.add_ethernet(phy=self.ethphy) + if with_etherbone: + self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( @@ -136,15 +139,20 @@ def main(): builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--device", default="LFE5UM5G", help="ECP5 device (LFE5UM5G (default) or LFE5UM)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--device", default="LFE5UM5G", help="ECP5 device (LFE5UM5G (default) or LFE5UM)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") args = parser.parse_args() + assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), - device = args.device, - with_ethernet = args.with_ethernet, - toolchain = args.toolchain, + device = args.device, + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_phy = args.eth_phy, + toolchain = args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}