From 91981b960c949aa117507488da2bccb2728040ad Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 31 Mar 2020 16:54:38 +0200 Subject: [PATCH] soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce. This reduces logic a bit. It does not make large difference on usual design with only 1 UART, but is interesting on designs with hundreds of UARTs used to "document" FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py) --- litex/soc/cores/uart.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 4eda4c27e..e6315016d 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -35,12 +35,12 @@ class RS232PHYRX(Module): # # # uart_clk_rxen = Signal() - phase_accumulator_rx = Signal(32) + phase_accumulator_rx = Signal(32, reset_less=True) rx = Signal() rx_r = Signal() - rx_reg = Signal(8) - rx_bitcount = Signal(4) + rx_reg = Signal(8, reset_less=True) + rx_bitcount = Signal(4, reset_less=True) rx_busy = Signal() rx_done = self.source.valid rx_data = self.source.data @@ -87,12 +87,12 @@ class RS232PHYTX(Module): # # # uart_clk_txen = Signal() - phase_accumulator_tx = Signal(32) + phase_accumulator_tx = Signal(32, reset_less=True) pads.tx.reset = 1 - tx_reg = Signal(8) - tx_bitcount = Signal(4) + tx_reg = Signal(8, reset_less=True) + tx_bitcount = Signal(4, reset_less=True) tx_busy = Signal() self.sync += [ self.sink.ready.eq(0),