From 922f85e64b5609eb74012d7bc7d883756276fe46 Mon Sep 17 00:00:00 2001 From: Vamsi Vytla Date: Wed, 3 Mar 2021 10:50:58 -0800 Subject: [PATCH] litex/soc/cores/ussysmon.py: ADC transfer function --- litex/soc/cores/ussysmon.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/ussysmon.py b/litex/soc/cores/ussysmon.py index 04dc8d099..9fd4da3c4 100644 --- a/litex/soc/cores/ussysmon.py +++ b/litex/soc/cores/ussysmon.py @@ -103,7 +103,7 @@ class USSYSMON(Module, AutoCSR): self.sync += [ If(self.drdy, Case(channel, dict( - (k, v.status.eq(self.do >> 4)) + (k, v.status.eq(self.do >> 6)) for k, v in channels.items())) ) ]